MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 173
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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4.4.3.6
The MPC8544E can be configured with different I/O ports active.
I/O ports and bit rates (and required reference clocks) that are possible for the PCI Express interfaces.
Freescale Semiconductor
TSEC3_TXD[6:4]
Default (111)
Functional
Signal
I/O Port Selection
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reset Configuration
cfg_IO_ports[0:2]
Name
Table 4-14. I/O Port Selection
(Binary)
Value
000
001
010
011
100
101
All three PCI Express ports powered down
SGMII ports powered down
All three PCI Express ports powered down
SGMII ports active
PCI Express port 1active
PCI Express ports 2 and 3 powered down
PCI Express 1:
RX lane[0:3] → SD1_RX[0:3],
TX lane[0:3] → SD1_TX[0:3]
SGMII ports powered down
PCI Express port 1active
PCI Express ports 2 and 3 powered down
PCI Express 1:
RX lane[0:3] → SD1_RX[0:3],
TX lane[0:3] → SD1_TX[0:3]
SGMII ports active
PCI Express ports 1 and 2 active
PCI Express port 3 powered down
PCI Express 1:
RX lane[0:3] → SD1_RX[0:3],
TX lane[0:3] → SD1_TX[0:3]
PCI Express 2:
RX lane[0:3] → SD1_RX[4:7],
TX lane[0:3] → SD1_TX[4:7]
SGMII ports powered down
PCI Express ports 1 and 2 active
PCI Express port 3 powered down
PCI Express 1:
RX lane[0:3] → SD1_RX[0:3],
TX lane[0:3] → SD1_TX[0:3]
PCI Express 2:
RX lane[0:3] → SD1_RX[4:7],
TX lane[0:3] → SD1_TX[4:7]
SGMII ports active
Table 4-14
Meaning
shows the configuration of
Reset, Clocking, and Initialization
4-15
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