MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 191

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.3
Key features of the e500 are summarized as follows:
Freescale Semiconductor
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32-bit architecture
Additional categories (formerly referred to as APUs)
Branch target buffer (BTB) locking is specific to the e500. BTB locking gives the user the ability
to lock, unlock, and invalidate BTB entries; further information is provided in
(see EREF: a Reference for Freescale Book E and the e500 Core) defines the following:
— Integer select. This instruction is now part of the Power Architecture technology base category.
— Performance monitor. The performance monitor facility provides the ability to monitor and
— Cache locking. Allows instructions and data to be locked into their respective caches on a cache
— Machine check. The machine check interrupt is treated as a separate level of interrupt. It uses
— Single-precision embedded scalar and vector floating-point instructions, listed in
— Signal processing engine (SPE). Note that the SPE is not a separate unit; SPE computational and
Features
count predefined events such as processor clocks, misses in the instruction cache or data cache,
types of instructions decoded, or mispredicted branches. The count of such events can be used
to trigger the performance monitor exception. Additional performance monitor registers
(PMRs) similar to SPRs are used to configure and track performance monitor operations. These
registers are accessed with the Move to PMR and Move from PMR instructions (mtpmr and
mfpmr). See
block basis. Locking is performed by a set of touch and lock set instructions. This functionality
can be enabled for user mode by setting MSR[UCLE]. The feature also provides resources for
detecting and handling overlocking conditions.
its own save and restore registers (MCSRR0 and MCSRR1) and Return from Machine Check
Interrupt (rfmci) instruction. See
logical instructions are executed in the simple and multiple-cycle units used by all other
computational and logical instructions, and 64-bit loads and stores are executed in the common
LSU.
support operations on the upper halves of the GPRs.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
The SPE APU and the two single-precision floating-point APUs were
combined in the original implementation of the e500 v1, as shown in
Figure
Figure 5-1
Original SPE
Definition
5-2.
Section 5.12, “Performance Monitoring.”
shows how execution logic for SU1, the MU, and the LSU is replicated to
Figure 5-2. Vector and Floating-Point APUs
SPE vector instructions ev…
Vector single-precision floating-point evfs…
Scalar single-precision floating-point efs…
Scalar double-precision floating-point efd…
Vector and Floating-Point APUs
Section 5.8, “Interrupts and Exception Handling.”
NOTE
e500 v1 e500 v2
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√
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√
Table 5-5.
Core Complex Overview
Table
The EIS
5-4.
5-5