MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 263

MPU POWERQUICC III 783-PBGA

MPC8544VTALF

Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8544VTALF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
6.13.3
6.13.4
6.14
Freescale Semiconductor
SPR 312 (IAC1); SPR 313 (IAC2)
SPR 316 (DAC1); SPR 317 (DAC2)
Reset
Reset
Reset
Reset
SPR: 512
Bits
32
33
W
W
W
W
R
R
R
R
SOVH OVH FGH FXH FINVH FDBZH FUNFH FOVFH
32
32
SOV
32
48
Name
SOVH
OVH
Signal Processing and Embedded Floating-Point Status
and Control Register (SPEFSCR)
OV
Instruction Address Compare Registers (IAC1–IAC2)
Data Address Compare Registers (DAC1–DAC2)
33
49
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 6-56. Signal Processing and Embedded Floating-Point Status and
until it is cleared by an mtspr[SPEFSCR].
Integer overflow high. An overflow occurred in the upper half of the register while executing a SPE integer
instruction
Summary integer overflow high. Set whenever an instruction (except mtspr) sets OVH. SOVH remains set
FG
34
50
Figure 6-54. Instruction Address Compare Registers (IAC1–IAC2)
High-Word Error Bits
Figure 6-55. Data Address Compare Registers (DAC1–DAC2)
FX
35
51
FINV
36
52
Table 6-39. SPEFSCR Field Descriptions
FDBZ
37
53
Control Register (SPEFSCR)
FUNF
38
54
Instruction address
FOVF — FINXE FINVE FDBZE FUNFE FOVFE
Data address
39
55
All zeros
All zeros
All zeros
All zeros
40
56
Function
41
57
FINXS FINVS FDBZS FUNFS FOVFS
42
58
Enable Bits
43
59
Status Bits
Access: Supervisor read/write
Access: Supervisor read/write
44
60
Core Register Summary
45
61
Access: User mixed
46
62
FRMC
61 62 63
MODE
47
63
6-45
63

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