MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 937

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 15-167
Freescale Semiconductor
describes the register initializations required to configure the eTSEC in 8-bit FIFO mode.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
(Rx enable = 1, Tx enable = 1, enable flow control and CRC, 8-bit mode)
RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Table 15-167. 8-Bit FIFO Mode Register Initialization Steps
TBASE0–TBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Initialize (Empty) Receive Descriptor ring and fill with empty buffers
Initialize (Empty) transmit descriptor ring and fill buffers with data
MACCFG2[0000_0000_0000_0000_0111_0000_0000_0000]
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
FIFOCFG[0000_0000_0000_0000_1100_0000_0000_0000]
FIFOCFG[0000_0000_0000_0000_0000_0000_0000_1000]
FIFOCFG[0000_0000_0000_0000_0011_0000_1101_1000]
ECNTRL[0000_0000_0000_0000_1000_0000_0000_0000]
(Reset RX = 1, reset Tx = 1, Rx enable = 0, Tx enable = 0)
(Reset RX = 0, reset Tx = 0, Rx enable = 0, Tx enable = 0)
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
(Used to set up FIFO mode = 1, and statistics enable = 0)
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Ensure MACCFG2 is set to default values.
Initialize DMACTRL (Optional)
Enable Rx and Tx over FIFO,
Initialize RBASE0–RBASE7,
Initialize TBASE0–TBASE7,
Initialize RCTRL (Optional)
Initialize IMASK (Optional)
Enable Transmit Queues
Enable Receive Queues
Clear FIFO Soft_Reset,
Clear IEVENT register,
Set FIFO Soft_Reset,
Initialize ECNTRL,
Initialize RQUEUE
Initialize TQUEUE
Enhanced Three-Speed Ethernet Controllers
15-205