MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 180

MPU POWERQUICC III 783-PBGA

MPC8544VTALF

Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8544VTALF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Part Number:
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Manufacturer:
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Quantity:
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Reset, Clocking, and Initialization
4.4.3.19
The PCI arbiter configuration inputs, shown in
value latched on these signals during POR are accessible through the PORDEVSR described in
Section 19.4.1.4, “POR Device Status Register (PORDEVSR).”
4.4.3.20
The memory debug configuration input, shown in
memory controller) are driven onto the MSRCID and MDVAL debug signals. Note that the value latched
on this signal during POR is accessible through the memory-mapped PORDBGMSR (POR debug mode
register) described in
4.4.3.21
The DDR debug configuration input, shown in
in which the DDR SDRAM source ID field and data valid strobe are driven onto the ECC pins. ECC
checking and generation are disabled in this case. ECC signals driven from the SDRAMs must be
electrically disconnected from the ECC I/O pins of the MPC8544E in this mode.
4-22
Functional Signal
Functional
PCI_GNT2
Functional
Default (1)
Default (1)
MSRCID0
Signal
Signal
PCI_GNT1
Default (1)
Reset Configuration
PCI Arbiter Configuration
Memory Debug Configuration
DDR Debug Configuration
Reset Configuration
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
cfg_mem_debug
cfg_pci_arb
Name
Reset Configuration
Name
Section 19.4.1.5, “POR Debug Mode Status Register (PORDBGMSR).”
cfg_pci_impd
Name
(Binary)
Table 4-29. Memory Debug Configuration
Value
(Binary)
Table 4-28. PCI Arbiter Configuration
0
1
Value
0
1
Table 4-27. PCI I/O Impedance
The on-chip PCI arbiter is disabled. External arbitration is required.
The on-chip PCI arbiter is enabled (default).
(Binary)
Value
Debug information from the local bus controller (LBC) is driven on the
MSRCID and MDVAL signals
Debug information from the DDR SDRAM controller is driven on the
MSRCID and MDVAL signals (default).
0
1
Table
Table
Table
25-Ω I/O drivers are used on the PCI interface.
42-Ω I/O drivers are used on the PCI interface (default).
4-30, enables a DDR memory controller debug mode
4-28, enable the on-chip PCI arbiter. Note that the
4-29, selects which debug outputs (DDR or LBC
Meaning
Meaning
Meaning
Freescale Semiconductor

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