MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1221

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
PCI clock cycles
PCI inbound memory reads
PCI inbound memory writes
PCI inbound config reads
PCI inbound config writes
PCI outbound memory reads
PCI outbound memory writes
PCI outbound I/O reads
PCI outbound I/O writes
PCI outbound config reads
PCI outbound config writes
PCI inbound 32-bit read data beats
PCI inbound 32-bit write data beats
PCI outbound 32-bit read data beats
PCI outbound 32-bit write data beats
PCI total transactions
PCI inbound purgeable reads
PCI inbound (speculative reads)
purgeable reads discarded
PCI idle cycles
PCI dual address cycles
PCI internal cycles
PCI inbound memory read
PCI inbound memory readline
PCI inbound memory read multiple
PCI outbound memory reads
PCI outbound memory read lines
PCI wait
PCI snoopable
PCI write stash
Event Counted
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 20-10. Performance Monitor Events (continued)
Number
C1:126
C2:101
C3:127
C4:101
C3:101
C4:102
C2:102
C3:102
C4:103
C8:127
C2:104
C3:103
C2:108
C3:106
C4:107
C5:100
C2:106
Ref:28
C5:94
C6:96
C7:90
C8:90
C1:94
C7:93
C2:66
C1:95
C1:98
C1:99
C1:96
PCI Events
—
Includes all read types.
—
—
—
Includes all read types.
Number of PCI outbound memory writes or number of PCI-X
outbound memory writes attempted.
—
—
Number of PCI outbound config reads OR number of PCI-X
outbound config reads attempted.
—
—
—
—
—
Includes 32- and 64-bit transactions.
—
—
—
—
—
—
—
—
Number of PCI outbound memory reads or number of PCI-X
outbound memory DWORD reads attempted.
Number of PCI outbound memory read lines or number of
PCI-X outbound memory burst reads attempted.
PCI_IRDY, PCI_TRDY not both asserted
—
—
Description of Event Counted
Device Performance Monitor
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