MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 431

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 10-29
10.3.4.2
Figure 10-26
Table 10-30
Freescale Semiconductor
0–31
Bits Name
12–15 TIMER Timer interrupts 0–3
16–19 MSG Message interrupts 0–3
20–31
Offset PM0MR1: 0x4_1360, PM1MR1: 0x4_1380, PM2MR1: 0x4_13A0, PM3MR1: 0x4_13C0
Reset 1
8–11
Bits
0–7
W
R
INT
Name
0
EXT External interrupts IRQ[0:11]
IPI
—
1
Internal interrupts 0–31
0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.
1 The corresponding interrupt does not generate a performance monitor event.
describes the PMnMR0 fields.
describes the PMnMR1 fields.
shows the PM0MR1, PM1MR1, PM2MR1, and PM3MR1 registers.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
IPI interrupts 0–3
0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.
1 The corresponding interrupt does not generate a performance monitor event.
0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.
1 The corresponding interrupt does not generate a performance monitor event.
0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.
1 The corresponding interrupt does not generate a performance monitor event.
0 The corresponding interrupt source generates a performance monitor event when the interrupt occurs.
1 The corresponding interrupt does not generate a performance monitor event.
1
Performance Monitor n Mask Registers 1 (PM n MR1)
1
Figure 10-26. Performance Monitor n Mask Registers 1 (PM n MR1)
1
1
1
1
Table 10-29. PM n MR0 Field Descriptions
1
Table 10-30. PM n MR1 Field Descriptions
1
1
1
1
1
1
Description
Description
1
INT
1
1
1
1
1
1
1
Programmable Interrupt Controller
1
1
1
1
Access: Read/Write
1
1
1
1
10-33
31
1