MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1087

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
24–31
Bits
13
14
15
16
17
18
19
20
21
22
23
CRSNCIE CRS non configuration interrupt enable. When this bit is set and PEX_ERR_DR[CRSNC] = 1 will generate
CRSTIE
IOIEPIE
ICCAIE
CIEPIE
IACAIE
OACIE
IOISIE
IOIAIE
Name
MISIE
CISIE
Table 18-24. PCI Express Error Interrupt Enable Register Field Descriptions (continued)
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
an interrupt.
1 Enable CRS non configuration interrupt generation
0 Disable CRS non configuration interrupt generation
Invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA configuration access interrupt enable. When set and
PEX_ERR_DR[ICCA]=1 will generate an interrupt.
1 Enable invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation
0 Disable invalid PEX_CONFIG_ADDR/PEX_CONFIG_DATA access interrupt generation.
Invalid ATMU configuration access. When set and PEX_ERR_DR[IACA]=1 will generate an interrupt.
1 Enable invalid ATMU configuration access interrupt generation
0 Disable invalid ATMU configuration access interrupt generation
CRS thresholded interrupt enable. When set and PEX_ERR_DR[CRST]=1 will generate an interrupt.
1 Enable CRS threshold interrupt generation
0 Disable CRS threshold interrupt generation
Message invalid size interrupt enable. When set and PEX_ERR_DR[MIS]=1 will generate an interrupt.
1 Enable invalid outbound message size interrupt generation
0 Disable invalid outbound message size interrupt generation
I/O invalid size interrupt enable. When set and PEX_ERR_DR[IOIS]=1 will generate an interrupt.
1 Enable invalid outbound I/O size interrupt generation
0 Disable invalid outbound I/O size interrupt generation
Configuration invalid size interrupt enable. When set and PEX_ERR_DR[CIS]=1 will generate an interrupt.
1 Enable invalid outbound configuration size interrupt generation
0 Disable invalid outbound configuration size interrupt generation
Configuration invalid EP interrupt enable. When set and PEX_ERR_DR[CIEP]=1 will generate an
interrupt.
1 Enable outbound configuration transaction while in EP mode interrupt generation
0 Disable outbound configuration transaction in EP mode interrupt generation
I/O invalid EP interrupt enable. When set and PEX_ERR_DR[IOIEP]=1 will generate an interrupt.
1 Enable outbound I/O transaction EP mode interrupt generation
0 Disable outbound I/O transaction EP mode interrupt generation
Outbound ATMU crossing interrupt enable. When set and PEX_ERR_DR[OAC]=1 will generate an
interrupt.
1 Enable outbound crossing ATMU interrupt generation
0 Disable outbound crossing ATMU interrupt generation
I/O address invalid enable. When set and PEX_ERR_DR[IOIA]=1 will generate an interrupt.
1 Enable greater than 4G I/O address interrupt generation
0 Disable greater than 4G I/O address interrupt generation
Reserved
Description
PCI Express Interface Controller
18-33