MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 268

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Core Register Summary
6.15.2
6-50
Reset
56–63
Bits
Bits
55
32
33
34
35
36
W
R
PMLCa0 (PMR144)
PMLCa1 (PMR145)
PMLCa2 (PMR146)
PMLCa3 (PMR147)
FC FCS FCU FCM1 FCM0 CE
32
Figure 6-59. Local Control A Registers (PMLCa0–PMLCa3), User Local Control A Registers
Name
FCM1 Freeze counter while mark = 1
FCM0 Freeze counter while mark = 0
FCU
Name
FCS
TBEE
FC
33
—
Local Control A Registers
(PMLCa0–PMLCa3, UPMLCa0–UPMLCa3)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
34
Freeze counter
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented.
Freeze counter in supervisor state
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PR] = 0.
Freeze counter in user state
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PR] = 1.
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PMM] = 1.
0 The PMC is incremented (if permitted by other PM control bits).
1 The PMC is not incremented if MSR[PMM] = 0.
0 Exceptions from time base transition events are disabled.
1 Exceptions from time base transition events are enabled. A timebase transition is signaled to the
Time base transition event exception enable.
Reserved, should be cleared.
performance monitor if the TB bit specified in PMGC0[TBSEL] changes from 0 to 1. Timebase transition
events can be used to freeze the counters (PMGC0[FCECE]) or signal an exception (PMGC0[PMIE]).
Changing PMGC0[TBSEL] while PMGC0[TBEE] is enabled may cause a false 0 to 1 transition that
signals the specified action (freeze, exception) to occur immediately. Although the interrupt signal
condition may occur with MSR[EE] = 0, the interrupt cannot be taken until MSR[EE] = 1.
35
36
Table 6-43. PMGC0 Field Descriptions (continued)
Table 6-44. PMLCa0–PMLCa3 Field Descriptions
UPMLCa0 (PMR128)
UPMLCa1 (PMR129)
UPMLCa2 (PMR130)
UPMLCa3 (PMR131)
37 38
—
40 41
(UPMLCa0–UPMLCa3)
EVENT
All zeros
Description
Description
47 48
Access: PMLCa0–PMLCa3: Supervisor read/write
UPMLCa0–UPMLCa3: Supervisor/user read only
—
Freescale Semiconductor
63