MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 42

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Paragraph
Number
19.4.1.18
19.4.1.19
19.4.1.20
19.4.1.21
19.4.1.22
19.4.1.23
19.4.1.24
19.4.1.25
19.4.1.26
19.5
19.5.1
19.5.1.1
19.5.1.2
19.5.1.3
19.5.1.4
19.5.1.5
19.5.1.5.1
19.5.1.5.2
19.5.1.5.3
19.5.1.6
19.5.1.7
19.5.1.8
19.5.1.8.1
19.5.1.8.2
19.5.1.9
19.5.1.10
19.5.1.11
19.5.2
19.5.3
20.1
20.1.1
20.1.2
20.2
20.3
20.3.1
20.3.2
20.3.2.1
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MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Functional Description................................................................................................. 19-27
Introduction.................................................................................................................... 20-1
Signal Descriptions ........................................................................................................ 20-3
Memory Map and Register Definition........................................................................... 20-3
Power Management ................................................................................................. 19-27
General-Purpose I/O Signals ................................................................................... 19-35
Interrupt and Local Bus Signal Multiplexing .......................................................... 19-35
Overview.................................................................................................................... 20-2
Features...................................................................................................................... 20-3
Register Summary...................................................................................................... 20-3
Control Registers ....................................................................................................... 20-5
Reset Control Register (RSTCR)......................................................................... 19-20
LBC Voltage Select Control Register (LBCVSELCR) ....................................... 19-20
DDR Calibration Status Register (DDRCSR) ..................................................... 19-21
DDR Control Driver Register (DDRCDR).......................................................... 19-21
DDR Clock Disable Register (DDRCLKDR) ..................................................... 19-22
Clock Out Control Register (CLKOCR) ............................................................. 19-23
SerDes 1 Control Register 1 (SRDS1CR1) ......................................................... 19-24
SerDes 2 Control Register 1 (SRDS2CR1) ......................................................... 19-25
SerDes 2 Control Register 3 (SRDS2CR3) ......................................................... 19-26
Relationship Between Core and Device Power Management States................... 19-27
CKSTP_IN is Not Power Management ............................................................... 19-28
Dynamic Power Management.............................................................................. 19-28
Shutting Down Unused Blocks............................................................................ 19-28
Software-Controlled Power-Down States............................................................ 19-29
Power Management Control Fields ..................................................................... 19-30
Power-Down Sequence Coordination.................................................................. 19-30
Interrupts and Power Management ...................................................................... 19-33
Snooping in Power-Down Modes........................................................................ 19-34
Software Considerations for Power Management ............................................... 19-34
Requirements for Reaching and Recovering from Sleep State............................ 19-34
Performance Monitor Global Control Register (PMGC0) .................................... 20-5
Doze Mode ...................................................................................................... 19-29
Nap Mode ........................................................................................................ 19-29
Sleep Mode ...................................................................................................... 19-29
Interrupts and Power Management Controlled by MSR[WE] ........................ 19-33
Interrupts and Power Management Controlled by POWMGTCSR................. 19-33
Device Performance Monitor
Contents
Chapter 20
Title
Freescale Semiconductor
Number
Page