MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1193

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.5
This section describes the global utilities from a functional perspective.
19.5.1
The MPC8544E has features to minimize power consumption at several levels. Dynamic power
management locally minimizes power consumption when a block is idle. Software can also shut down
clocks to individual blocks when they are not needed through a memory-mapped register (DEVDISR).
Additionally, software running on the e500 core can access the core’s SPRs to put the device into doze,
nap, or sleep power down state. Finally, software can access a memory-mapped register (POWMGTCR)
in the global utilities block to put the device in the doze or sleep states.
Note that the software that writes to either DEVDISR or POWMGTCR can be running either on the e500
core or on an external master that can write to the MPC8544E memory-mapped registers through the PCI
interfaces.
These features are described in further detail in this section.
19.5.1.1
The MPC8544E has three low-power states: doze, nap, and sleep. The mapping of core and device power
management states is shown in
core.
For each operating state represented in the diagram, the core’s state is listed first, with the corresponding
state of the MPC8544E shown beneath it in parenthesis. Note that there are many other variables that
control the state transitions between MPC8544E power management states. These additional variables are
described in more detail in
Freescale Semiconductor
Functional Description
Power Management
Relationship Between Core and Device Power Management States
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 19-27. e500 Core Power Management State Diagram
Section 19.5.1.7, “Power-Down Sequence Coordination.”
core_stop & core_halt
Figure 19-27
¬ core_tben
core_halt
showing state transitions from the perspective of the e500
Core-Stopped
Core-Stopped
Core-Halted
Full On
(Sleep)
(Doze)
(Nap)
¬ core_halt
¬ core_stop
core_tben
¬ core_halt
core_halt & ¬ core_stop
core_stop
¬ core_tben
Global Utilities
19-27