MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 751

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
0x2_45C0–
0x2_459C MAC11ADDR2*—MAC exact match address 11, part 2
0x2_45AC MAC13ADDR2*—MAC exact match address 13, part 2
0x2_45BC MAC15ADDR2*—MAC exact match address 15, part 2
0x2_467C
0x2_468C TR511—Transmit and receive 256- to 511-byte frame counter
0x2_469C RBYT—Receive byte counter
0x2_46AC RBCA—Receive broadcast packet counter
0x2_46BC RALN—Receive alignment error counter
0x2_46C0 RFLR—Receive frame length error counter
0x2_46C4 RCDE—Receive code error counter
0x2_46C8 RCSE—Receive carrier sense error counter
0x2_45A0 MAC12ADDR1*—MAC exact match address 12, part 1
0x2_45A4 MAC12ADDR2*—MAC exact match address 12, part 2
0x2_45A8 MAC13ADDR1*—MAC exact match address 13, part 1
0x2_45B0 MAC14ADDR1*—MAC exact match address 14, part 1
0x2_45B4 MAC14ADDR2*—MAC exact match address 14, part 2
0x2_45B8 MAC15ADDR1*—MAC exact match address 15, part 1
0x2_46A0 RPKT—Receive packet counter
0x2_46A4 RFCS—Receive FCS error counter
0x2_46A8 RMCA—Receive multicast packet counter
0x2_46B0 RXCF—Receive control frame packet counter
0x2_46B4 RXPF—Receive PAUSE frame packet counter
0x2_46B8 RXUO—Receive unknown OP code counter
0x2_4594 MAC10ADDR2*—MAC exact match address 10, part 2
0x2_4598 MAC11ADDR1*—MAC exact match address 11, part 1
0x2_4680 TR64—Transmit and receive 64-byte frame counter
0x2_4684 TR127—Transmit and receive 65- to 127-byte frame counter
0x2_4688 TR255—Transmit and receive 128- to 255-byte frame counter
0x2_4690 TR1K—Transmit and receive 512- to 1023-byte frame counter
0x2_4694 TRMAX—Transmit and receive 1024- to 1518-byte frame counter
0x2_4698 TRMGV—Transmit and receive 1519- to 1522-byte good VLAN
eTSEC1
Offset
Reserved
frame count
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 15-4. Module Memory Map (continued)
Name
eTSEC Transmit and Receive Counters
1
eTSEC Receive Counters
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Enhanced Three-Speed Ethernet Controllers
2
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
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15.5.3.5.15/15-79
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15.5.3.6.11/15-85
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15.5.3.6.1/15-80
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Section/Page
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15-19