MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 693

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

14.4.4.6
Slow memory devices that take a long time to turn off their data bus drivers on read accesses should choose
some non-zero combination of ORn[TRLX] and ORn[EHTR]. The next accesses after a read access to the
slow memory device is delayed by the number of clock cycles specified in the ORn register in addition to
any existing bus turn around cycle.
14.4.4.7
Connecting the local bus UPM controller to a DRAM device requires a detailed examination of the timing
diagrams representing the possible memory cycles that must be performed when accessing this device.
This section shows timing diagrams for various UPM configurations, using fast-page mode DRAM as an
example, with LCRR[CLKDIV] = 4(clock ratio of 8) or 8(clock ratio of 16). These illustrative examples
may not represent the timing necessary for any specific device used with the LBC. Here, LGPL1 is
programmed to drive R/W of the DRAM, although any LGPLn signal may be used for this purpose.
Freescale Semiconductor
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Extended Hold Time on Read Accesses
Memory System Interface Example Using UPM
Local Bus Controller
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