MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 369

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.5.1
The DDR memory controller supports many different DDR SDRAM configurations. SDRAMs with
different sizes can be used in the same system. Sixteen multiplexed address signals and three logical bank
select signals support device densities from 64 Mbits to 4 Gbits. Four chip select (CS) signals support up
to two DIMMs of memory. The DDR SDRAM physical banks can be built from standard memory modules
or directly-attached memory devices. The data path to individual physical banks is 64 or 32 bits wide, 72
or 40 bits with ECC. The DDR memory controller supports physical bank sizes from 16 Mbytes to
4 Gbytes. The physical banks can be constructed using x8, x16, or x32 memory devices. The memory
technologies supported are 64 Mbits, 128 Mbits, 256 Mbits, 512 Mbits, 1 Gbit, 2 Gbits, and 4 Gbits. Nine
data qualifier (DQM) signals provide byte selection for memory accesses.
When ECC is enabled, all memory accesses are performed on double-word boundaries (that is, all DQM
signals are set simultaneously). However, when ECC is disabled, the memory system uses the DQM
signals for byte lane selection.
Table 9-38
MDQS[0:7], and MDQ[0:63] when DDR SDRAM memories are used with x8 or x16 devices.
9.5.1.1
Although the DDR memory controller multiplexes row and column address bits onto 1616 memory
address signals and 3 logical bank select signals, a physical bank may be implemented with memory
devices requiring fewer than 31 address bits. The physical bank may be configured to provide from 12 to
16 row address bits, plus 2 or 3 logical bank-select bits and from 8–11 column address bits.
Freescale Semiconductor
shows the DDR memory controller’s relationships between data byte lane0–7, MDM[0:7],
DDR SDRAM Interface Operation
Supported DDR SDRAM Organizations
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
An 8-bit DDR SDRAM device has a DQM signal and eight data signals
(DQ[0:7]). A 16-bit DDR SDRAM device has two DQM signals associated
with specific halves of the 16 data signals (DQ[0:7] and DQ[8:15]).
Data Byte Lane
0 (MSB)
7 (LSB)
1
2
3
4
5
6
Table 9-38. Byte Lane to Data Relationship
Data Bus Mask
MDM[0]
MDM[1]
MDM[2]
MDM[3]
MDM[4]
MDM[5]
MDM[6]
MDM[7]
NOTE
Data Bus Strobe Data Bus 64-Bit Mode
MDQS[0]
MDQS[1]
MDQS[2]
MDQS[3]
MDQS[4]
MDQS[5]
MDQS[6]
MDQS[7]
MDQ[16:23]
MDQ[24:31]
MDQ[32:39]
MDQ[40:47]
MDQ[48:55]
MDQ[56:63]
MDQ[8:15]
MDQ[0:7]
DDR Memory Controller
9-45