MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 117

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.3.14
In order to reduce the strain on core interconnects with the addition of new functional blocks in this
generation of the PowerQUICC family, a multi-port, on-chip, non-blocking crossbar switch fabric called
OCeaN (on-chip network) has been provided. The switch fabric serves to decrease contention and increase
bandwidth. This non-blocking crossbar fabric allows full-duplex port communication with independent
per-port transaction queuing and flow control.
1.3.15
The MPC8544E DMA engine is capable of transferring blocks of data from any legal address range to any
other legal address range. Therefore, it can perform a DMA transfer between any of its I/O or memory
ports or even between two devices or locations on the same port.
The four-channel DMA controller allows chaining (both extended and direct) through local
memory-mapped chain descriptors. Scattering, gathering, and misaligned transfers are supported. In
addition, advanced capabilities such as stride transfers and complex transaction chaining are supported.
DMA transfers can be initiated by a single write to a configuration register. There is also support for
external control of transfers using DMA_DREQ, DMA_DACK, and DMA_DDONE handshake signals.
Interrupts are provided on a completed segment, link, list, chain, or on an error condition. Coherency is
selectable and hardware enforced (snoop/no snoop).
1.3.16
The MPC8544E has a 32-bit PCI controller that is compatible with the PCI Local Bus Specification,
Revision 2.2. The controller can function as a host bridge or as an agent interface.
As a master, the MPC8544E supports read and write operations to PCI memory space, PCI I/O space, and
PCI configuration space. The MPC8544E can also generate PCI special-cycle and interrupt-acknowledge
commands. As an agent/target, the MPC8544E supports read and write operations to system memory as
well as configuration accesses.
An internal arbiter can be used to support up to five external masters. A round robin arbitration algorithm
with two priority levels is used.
1.3.17
The MPC8544E supports a PCI Express interface compliant with the PCI Express Base Specification
Revision 1.0a. It is configurable at boot time to act as either root complex or endpoint.
The interface is selectable at boot time to support either 32 or 64-bit addressing. The maximum supported
packet payload size is 256 bytes.
The physical layer supports dual x4 links and a single x1 link.
Freescale Semiconductor
OceaN Switch Fabric
Integrated DMA
PCI Controller
PCI Express Interface
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Overview
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