MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 225

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 6-2
and embedded categories. Compilers should recognize the mnemonic names given in
parsing instructions.
Freescale Semiconductor
Abbreviation
MMUCSR0
MMUCFG
MCSRR0
MCSRR1
L1CFG0
L1CFG1
L1CSR0
L1CSR1
MCARU
BBEAR
BUCSR
IVOR32
IVOR33
IVOR34
IVOR35
BBTAR
MCAR
MCSR
MAS0
MAS1
MAS2
MAS3
MAS4
MAS6
MAS7
HID0
HID1
SPR
describes the implementation-specific SPRs and SPRs defined by categories other than the base
Branch buffer entry address register
Branch buffer target address register
Branch unit control and status register
Hardware implementation dependent reg 0
Hardware implementation dependent reg 1
SPE unavailable interrupt offset
Floating-point data exception interrupt offset
Floating-point round exception interrupt offset
Performance monitor
L1 cache configuration register 0
L1 cache configuration register 1
L1 cache control and status register 0
L1 cache control and status register 1
MMU assist register 0
MMU assist register 1
MMU assist register 2
MMU assist register 3
MMU assist register 4
MMU assist register 6
MMU assist register 7
Machine check address register
Machine check address register upper
Machine check syndrome register
Machine check save/restore register 0
Machine check save/restore register 1
MMU configuration register
MMU control and status register 0
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 6-2. Additional SPRs (by SPR Abbreviation)
Name
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SPR Number
1013
1008
1009
1010
1011
1015
1012
513
514
528
529
530
531
515
516
624
625
626
627
628
630
944
573
569
572
570
571
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read only
Read only
Read only
Read only
Read only
Access
Supervisor
Only
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
Table 6-2
Core Register Summary
6.12.5.1/6-35
6.12.5.2/6-35
6.12.5.3/6-36
6.12.5.4/6-37
6.12.5.5/6-38
6.12.5.6/6-38
6.12.5.7/6-39
6.7.1.7/6-18
6.7.2.3/6-21
6.7.2.3/6-21
6.7.2.4/6-21
6.7.2.1/6-20
6.7.2.2/6-20
6.10.1/6-25
6.10.2/6-26
6.11.3/6-30
6.11.4/6-31
6.11.1/6-28
6.11.2/6-29
6.12.3/6-32
6.12.2/6-32
6.9.1/6-23
6.9.2/6-23
6.9.3/6-24
Section/
when
Page
6-7