MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1042

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Bus Interface
Figure 17-56
respectively.
17.4.2.11 Configuration Cycles
This section describes PCI configuration cycles used for configuring standard PCI devices. The PCI
configuration space of any device is intended for configuration, initialization, and catastrophic
error-handling functions only. Access to the PCI configuration space should be limited to initialization and
error-handling software.
17.4.2.11.1 PCI Configuration Space Header
The first 64 bytes of the 256-byte configuration space consists of a predefined header that every PCI device
must support. The predefined header for all PCI devices is shown in
predefined header are defined the same for all PCI devices; the remaining 48 bytes of the header may have
differing layouts depending on the function of the device. Most PCI devices use the configuration header
17-58
PCI_C/BE[3:0]
PCI_C/BE[3:0]
PCI_DEVSEL
PCI_DEVSEL
PCI_AD[31:0]
PCI_AD[31:0]
PCI_FRAME
PCI_FRAME
PCI_TRDY
PCI_TRDY
PCI_IRDY
PCI_IRDY
PCI_CLK
PCI_CLK
and
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 17-57
Lo-Addr
Lo-Addr
x’D’
x’D’
Figure 17-56. DAC Single-Beat Write Example
show timing examples for single-beat DAC writes and burst DAC writes,
Figure 17-57. DAC Burst Write Example
Hi-Addr
Hi-Addr
Cmd
Cmd
Data1
BE’s1
Data2
BE’s2
Byte Enables
Data
Data3
BE’s3
Figure
Data4
BE’s4
17-58. The first 16 bytes of the
T/A
T/A
T/A
T/A
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