MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 789

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.5.3.3.6
RQFAR, shown in
received queue filer table. Each table entry occupies a pair of 32-bit words, denoted RQCTRL and
RQPROP. To access the RQCTRL and RQPROP words of entry n, write n to RQFAR. Then read or write
the indexed RQCTRL and RQPROP words by reading or writing the RQFCR and RQFPR registers,
respectively.
Freescale Semiconductor
10–15
16–17
18–23
24–25
26–31
Bits
8–9
Offset eTSEC1:0x2_4334; eTSEC3:0x2_5334
Reset
W
R
B1OFFSET Offset relative to the header defined by B1CTL that locates byte 1 of property ARB. An effective offset
B2OFFSET Offset relative to the header defined by B2CTL that locates byte 2 of property ARB. An effective offset
B3OFFSET Offset relative to the header defined by B3CTL that locates byte 3 of property ARB. An effective offset
0
B1CTL
B2CTL
B3CTL
Name
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Receive Queue Filer Table Address Register (RQFAR)
Figure 15-27. Receive Queue Filer Table Address Register Definition
Figure
Location of byte 1 of property ARB.
00 Byte 1 is not extracted, and appears as zero in property ARB.
01 Byte 1 is located in the received frame at offset (B1OFFSET – 8) bytes from the first byte of the
10 Byte 0 is located in the received frame at offset B1OFFSET bytes from the byte after the last byte of
11 Byte 0 is located in the received frame at offset B1OFFSET bytes from the byte after the last byte of
of zero points to the first byte of the specified header.
Location of byte 2 of property ARB.
00 Byte 2 is not extracted, and appears as zero in property ARB.
01 Byte 2 is located in the received frame at offset (B2OFFSET – 8) bytes from the first byte of the
10 Byte 0 is located in the received frame at offset B2OFFSET bytes from the byte after the last byte of
11 Byte 0 is located in the received frame at offset B2OFFSET bytes from the byte after the last byte of
of zero points to the first byte of the specified header.
Location of byte 3 of property ARB.
00 Byte 3 is not extracted, and appears as zero in property ARB.
01 Byte 3 is located in the received frame at offset (B3OFFSET – 8) bytes from the first byte of the
10 Byte 0 is located in the received frame at offset B3OFFSET bytes from the byte after the last byte of
11 Byte 0 is located in the received frame at offset B3OFFSET bytes from the byte after the last byte of
of zero points to the first byte of the specified header.
Ethernet DA. A negative effective offset points to bytes of the standard Ethernet preamble.
the layer 2 header.
the layer 3 header.
Ethernet DA. A negative effective offset points to bytes of the standard Ethernet preamble.
the layer 2 header.
the layer 3 header.
Ethernet DA. A negative effective offset points to bytes of the standard Ethernet preamble.
the layer 2 header.
the layer 3 header.
15-27, contains the index of the current, indirectly accessible entry of the
Table 15-30. RBIFX Field Descriptions (continued)
—
All zeros
Description
Enhanced Three-Speed Ethernet Controllers
23 24
Access: Read/Write
RQFAR
15-57
31