MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 906

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
15.6.7.2
Data is presented to the eTSEC for transmission by arranging it in memory buffers referenced by the
TxBDs. In the TxBD the user initializes the R, PAD, W, I, L, TC, PRE, HFE, CF, and TOE bits and the
length (in bytes) in the first word, and the buffer pointer in the second word. Unused fields or fields written
by the eTSEC must be initialized to zero. For transmission over the FIFO interface the Ethernet specific
bits (PRE, DEF, HFE, LC, CF, RL and RC) have no meaning.
The eTSEC clears the R bit in the first word of the BD after it finishes using the data buffer. The transfer
status bits are then updated. Additional transmit frame status can be found in statistic counters in the MIB
block.
Software must expect eTSEC to prefetch multiple TxBDs, and for TCP/IP checksumming an entire frame
must be read from memory before a checksum can be computed. Accordingly, the R bit of the first TxBD
in a frame must not be set until at least one entire frame can be fetched from this TxBD onwards. If eTSEC
prefetches TxBDs and fails to reach a last TxBD (with bit L set), it will halt further transmission from the
current TxBD ring and report an underrun error as IEVENT[XFUN]; this indicates that an incomplete
frame was fetched, but remained unprocessed. The relevant TBPTR register points to the next unread
TxBD following the error.
Figure 15-135
15-174
Offset + 0
Offset + 2
Offset + 4
Offset + 6
R
0
Transmit Data Buffer Descriptors (TxBD)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PAD/CRC
defines the TxBD.
1
W
2
Beginning BD pointer
3
I
Figure 15-135. Transmit Buffer Descriptor
Figure 15-134. Buffer Descriptor Ring
L
4
W = 1
TC
5
4
PRE/DEF
0
TX DATA BUFFER POINTER
6
DATA LENGTH
3
0
7
HFE/LC CF/RL
8
1
2
9
10
11
RC
12
Freescale Semiconductor
13
TOE/UN
14
TR
15