MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 360

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DDR Memory Controller
ERR_DETECT is shown in
Table 9-31
9.4.1.26
The memory error disable register, shown in
controller’s error detection circuitry. Disabled errors are not detected or reported.
9-36
Offset 0xE40
Reset
25–27
Offset 0xE44
1–23
Reset
Bits
24
28
29
30
31
0
W w1c
R MME
W
R
0
0
Name
MME
MBE
MSE
ACE
SBE
—
—
—
describes the ERR_DETECT fields.
1
Memory Error Disable (ERR_DISABLE)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Multiple memory errors. This bit is cleared by software writing a 1.
0 Multiple memory errors of the same type were not detected.
1 Multiple memory errors of the same type were detected.
Reserved
Automatic calibration error. This bit is cleared by software writing a 1.
0 An automatic calibration error has not been detected.
1 An automatic calibration error has been detected.
Reserved
Multiple-bit error. This bit is cleared by software writing a 1.
0 A multiple-bit error has not been detected.
1 A multiple-bit error has been detected.
Single-bit ECC error. This bit is cleared by software writing a 1.
0 The number of single-bit ECC errors detected has not crossed the threshold set in ERR_SBE[SBET].
1 The number of single-bit ECC errors detected crossed the threshold set in ERR_SBE[SBET].
Reserved
Memory select error. This bit is cleared by software writing a 1.
0 A memory select error has not been detected.
1 A memory select error has been detected.
Figure 9-27. Memory Error Disable Register (ERR_DISABLE)
Figure 9-26. Memory Error Detect Register (ERR_DETECT)
Figure
Table 9-31. ERR_DETECT Field Descriptions
9-26.
—
—
Figure
All zeros
All zeros
9-27, allows selective disabling of the DDR
Description
23
ACED
23
24
ACE
w1c
25
24
—
25
27
—
MBED SBED — MSED
Freescale Semiconductor
27
28
Access: Read/Write
MBE SBE
w1c w1c
28
29
29
Access: w1c
30
—
30
MSE
31
w1c
31