MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 151

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
HRESET_REQ
GPOUT[0:7]
L1_TSTCLK
L2_TSTCLK
IRQ_OUT
LAD[0:31]
LCLK[0:2]
IIC1_SCL
IIC1_SDA
IIC2_SCL
IIC2_SDA
LA[28:31]
LUPWAIT
HRESET
LCS[0:4]
LDP[0:3]
IRQ[0:8]
LBCTL
LGPL0
LGPL1
LGPL2
LGPL3
LGPL4
/LGTA/
IRQ10
IRQ11
Name
LCKE
LCS5
LCS6
LCS7
IRQ9
LA27
LALE
/LOE
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
General-purpose output
Hard reset
Hard reset request
I
I
I
I
External interrupt 0–8
Interrupt output
External interrupt 10
External interrupt 11
External interrupt 9
L1 test clock
L2 test clock
Local bus port address
Local bus burst address
Local bus address/data
Local bus address latch enable
Local bus data buffer control
Local bus clock enable
Local bus clock
Local bus chip select 0–4
Local bus chip select 5
Local bus chip select 6
Local bus chip select 7
Local bus data parity
Local bus UPM general purpose
line 0
Local bus GP line 1
Local bus GP line 2
/output enable
Local bus GP line 3
Local bus GP line 4
/GPCM terminate access
/UPM wait
2
2
2
2
C serial clock
C serial data
C serial clock
C serial data
Table 3-2. MPC8544E Alphabetical Signal Reference (continued)
Description
purpose outputs
System control
System control
Functional
General-
Block
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
LBC
Test
Test
PIC
PIC
PIC
PIC
PIC
I
I
I
I
2
2
2
2
C
C
C
C
Alternate Function(s)
cfg_dram_type[0]
cfg_dram_type[1]
cfg_gpinput[0:31]
cfg_boot_seq[0]
DMA_DDONE3
DMA_DDONE2
cfg_sys_pll[0:3]
cfg_core_pll[1]
cfg_core_pll[0]
cfg_core_pll[2]
DMA_DREQ3
DMA_DREQ2
DMA_DACK3
cfg_cpu_boot
DMA_DACK2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Signals
No. of
32
8
1
1
1
1
1
1
9
1
1
1
1
1
1
4
1
1
1
1
3
5
1
1
1
4
1
1
1
1
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
Signal Descriptions
19.4.1.9/19-12
19-2/19-2
11-2/11-4
11-2/11-4
11-2/11-4
11-2/11-4
10-5/10-8
10-5/10-8
10-5/10-8
10-5/10-8
10-5/10-8
21-5/21-8
21-5/21-8
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
14-2/14-5
4-2/4-2
4-2/4-2
Table/
Page
3-11