MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1323

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

GPCM (LBC general-purpose chip-select machine), 14-36
GPOUT[24:31] (general-purpose outputs) signal, 19-3
GPRs (general-purpose registers), see e500 core, registers
Freescale Semiconductor
I/O impedance
interrupt and local bus signal multiplexing, 19-1, 19-13
interrupts and power management, 19-33
LBC voltage select, 19-20
machine check summary
memory map/register definition, 19-3
overview, 19-1
POR configuration
power management
processor version register (PVR), 19-18
register descriptions, 19-4
reset
signals summary, 19-2
snooping and power management, 19-34
system version register (SVR), 19-19
see also Local bus controller (LBC)
DDR controller, software select, 19-21
operation, 19-35
sources of mcp (MCPSUMR), 19-17
boot mode status register (PORBMSR), 19-6
debug mode status register (PORDBGMSR), 19-10
device status register (PORDEVSR), 19-8
I/O impedance status register (PORIMPSCR), 19-7
LAD[0:31] external system configuration (GPPORCR),
PLL status register (PORPLLSR), 19-4
see also Power-on reset (POR)
and interrupts, 19-33
and snooping, 19-34
block disable (DEVDISR), 19-14, 19-28
CKSTP_IN and core_stopped mode, 19-28
core and device control bits, 19-30
core and device modes, 19-27
device mode control and status register
doze mode, 19-29
dynamic power management, 19-28
features, 19-1
functional description, 19-27
nap mode, 19-29
power-down sequence, 19-30
sleep mode, 19-29, 19-34
software considerations, 19-34
by acronym, see Register Index
HRESET_REQ control, 19-20
RapidIO and PCI Express reset requests (RSTRSCR),
see also Signals, global utilities
4-23, 19-11
(POWMGTCSR), 19-16
19-18
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
H
Hash function, see eTSEC, hash function
HID0–1 (hardware implementation-dependent registers 0–1),
HRESET (hard reset) signal, 4-2, 4-8
HRESET_REQ (hard reset request) signal, 4-2, 11-18, 11-19
I
I/O impedance
I/O requirements, 19-34
I/O space
I
2
C interface
DDR controller driver select, 19-21
LBC and PCI/PCI-X signals
PCI/PCI-X interface (POR), 4-21
PCI/PCI-X addressing, 17-48
arbitration
block diagram, 11-1
boot sequencer
boot sequencer mode, 11-2, 11-17–11-20
calling address match condition, 11-6
clock control, 11-16
data transfer, 11-13
error handling
features, 11-2
frequency divider
functional description, 11-11
handshaking, 11-16
implementation details, 11-14
initialization/application information, 11-21–11-25
see e500 core, registers
control and status register (global utilities), 19-7
arbitration control, 11-15
loss of arbitration—forcing of slave mode, 11-24
procedure for arbitration, 11-15
POR configuration, 4-17
error condition behavior, 11-19
clock stretching, 11-17
clock synchronization, 11-16
input synchronization and digital filter, 11-16
master mode, 11-16
slave mode, 11-16
boot sequencer mode, 11-19
frequency divider register (I2CFDR), 11-6
address compare, 11-15
control transfer, 11-14
transaction monitoring, 11-14
boot sequencer mode, see I
generation of SCL when SDA low, 11-23
initialization sequence, 11-21
post-transfer software response, 11-22
mode
2
C interface, boot sequencer
Index-7