MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1036

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Bus Interface
Figure 17-51
Figure 17-52
17.4.2.8
A PCI transaction may be terminated by either the initiator or the target. The initiator is ultimately
responsible for concluding all transactions, regardless of the cause of the termination. All transactions are
concluded when PCI_FRAME and PCI_IRDY are both negated, indicating the bus is idle.
17.4.2.8.1
Normally, a master initiates termination by negating PCI_FRAME and asserting PCI_IRDY. This
indicates to the target that the final data phase is in progress. The final data transfer occurs when both
PCI_TRDY and PCI_IRDY are asserted. The transaction is considered complete when data is transferred
17-52
PCI_DEVSEL
PCI_FRAME
PCI_FRAME
PCI_EVSEL
PCI_TRDY
PCI_TRDY
PCI_C/BE
PCI_IRDY
PCI_C/BE
PCI_IRDY
Transaction Termination
illustrates a PCI single-beat write transaction.
illustrates a PCI burst write transaction.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
SYSCLK
SYSCLK
PCI_AD
PCI_AD
Master-Initiated Termination
Figure 17-51. PCI Single-Beat Write Transaction
ADDR
ADDR
CMD
CMD
Figure 17-52. PCI Burst Write Transaction
Byte Enables 1 Byte Enables 2
DATA1
DATA2
Byte Enables
DATA
Byte Enables 3
DATA3
DATA4
BEs 4
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