MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 254

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Core Register Summary
6.12.5.3
6-36
Reset
34–39
40–47
48–50
52–55
56–63
32–51
52–56
SPR 626
Bits
Bits
32
33
51
57
58
W
R
32
IPROT Invalidate protect. Set to protect this TLB entry from invalidate operations due the execution of tlbiva[x] (TLB1
TSIZE Translation size. Defines the TLB entry page size. For arrays that contain fixed-size TLB entries, TSIZE is
Name
Name
TID
TS
EPN
—
—
—
V
X0
X1
—
Table 6-29. MAS1 Field Descriptions—Descriptor Context and Configuration Control
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MAS Register 2 (MAS2)
TLB valid bit
0 This TLB entry is invalid.
1 This TLB entry is valid.
only). Note that not all TLB arrays are necessarily protected from invalidation with IPROT. Arrays that support
invalidate protection are denoted as such in the TLB configuration registers.
0 Entry is not protected from invalidation
1 Entry is protected from invalidation.
Reserved, should be cleared.
Translation identity. An 8-bit field that defines the process ID for this TLB entry. TID is compared with the
current process IDs of the three virtual address to be translated. A TID value of 0 defines an entry as global
and matches with all process IDs.
Reserved, should be cleared.
Translation space. This bit is compared with the IS or DS fields of the MSR (depending on the type of access)
to determine if this TLB entry may be used for translation.
ignored. For variable page size arrays, the page size is 4
0001 4 Kbytes
0010 16 Kbytes
0011 64 Kbytes
0100 256 Kbytes
0101 1 Mbyte
0110 4 Mbytes
Reserved, should be cleared.
Bits that represent offsets within a page are ignored and should be cleared.
Reserved for implementation-specific use
Effective page number. Depending on page size, only the bits associated with a page boundary are valid.
Implementation-dependent page attribute
Implementation-dependent page attribute
Table 6-30. MAS2 Field Descriptions—EPN and Page Attributes
EPN
Figure 6-45. MAS Register 2 (MAS2)
All zeros
Descriptions
Description
0111 16 Mbytes
1000 64 Mbytes
1001 256 Mbytes
1010 1 Gbyte (e500v2 only)
1011 4 Gbytes (e500v2 only)
TSIZE
51 52
Kbytes. The e500 supports the following sizes:
—
Access: Supervisor read/write
56 57
X0 X1 W
Freescale Semiconductor
58 59 60 61 62 63
I
M G E