MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 692

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Local Bus Controller
previous RAM word. When LUPWAIT is negated, the UPM continues normal functions. Note that during
WAIT cycles, the UPM does not handle data.
Figure 14-62
to hold the UPM in a particular state until LUPWAIT is negated. As the example shows, the LCSn and
LGPL1 states and the WAEN value are frozen until LUPWAIT is recognized as negated. WAEN is
typically set before the line that contains UTA = 1. Note that if WAEN and NA are both set in the same
RAM word, NA causes the burst address to increment once as normal regardless of whether the UPM
freezes.
14.4.4.5
If LUPWAIT is to be considered an asynchronous signal, which can be asserted/negated at any time, no
UPM RAM word must contain both WAEN = 1 and UTA = 1 simultaneously.
However, programming WAEN = 1 and UTA = 1 in the same RAM word allows UPM to treat LUPWAIT
as a synchronous signal, which must meet set-up and hold times in relation to the rising edge of the bus
clock. In this case, as soon as UPM samples LUPWAIT negated on the rising edge of the bus clock, it
immediately generates an internal transfer acknowledge, which allows a data transfer one bus clock cycle
later. The generation of transfer acknowledge is early because LUPWAIT is not re-synchronized, and the
acknowledge occurs regardless of whether UPM was already frozen in WAIT cycles or not. This feature
allows the synchronous negation of LUPWAIT to affect a data transfer, even if UTA, WAEN, and LAST
are set simultaneously.
14-72
shows how the WAEN bit in the word read by the UPM and the LUPWAIT signal are used
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
LUPWAIT
Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge
LGPL1
WAEN
LCLK
LCS n
T1
T2
T3
T4
TA
c1 c2 c3 c4 c5 c6 c7 c8
Word n
A
Figure 14-62. Effect of LUPWAIT Signal
Word n+1
B
c9 c10 c11
Word n+2
C
c12
Wait
Freescale Semiconductor
Word n+3
c13 c14
D