MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 674
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Local Bus Controller
14.4.3.7.5
This parameter, controlled by LSDMR[RFRC], defines the earliest timing for an ACTIVATE or
REFRESH command after a REFRESH command to the same SDRAM device.
14.4.3.7.6
If the additional delay of any buffers placed on the command strobes (LSDRAS, LSDCAS, LSDWE, and
LSDA10), is endangering the device setup time, LSDMR[BUFCMD] should be set. Setting this bit causes
the memory controller to add LCRR[BUFCMDC] extra bus cycles to the assertion of SDRAM control
signals (LSDRAS, LSDCAS, LSDWE, and LSDA10) for each SDRAM command.
14-54
LSDDQM[0:3]
LSDDQM
LSDRAS
LSDCAS
LAD[0:31]
LSDWE
LSDRAS
LSDCAS
LSDWE
LCLK
LCS n
LALE
LAD
LCLK
LCS n
LALE
ZZZZZZ RAS ADD
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Refresh Recovery Interval (RFRC)
External Address and Command Buffers (BUFCMD)
Setup Cycle
ZZZZZZZZ
Command
XXXXXXXX
Figure 14-41. BUFCMD = 1, LCRR[BUFCMDC] = 2
Command (If Needed)
1111
PRECHARGE ALL
Figure 14-40. RFRC = 4 (6 Clock Cycles)
CAS ADD
PRETOACT = 3
XXXX
Setup Cycle
Command
AUTO REFRESH
D0
Command
1111
1111
D1
0000
D2
RFRC = 4 (6 Clocks)
D3
RAS ADD
XXXX
Freescale Semiconductor
ZZZZZZZZ
1111
ACTIVATE
Command
CAS ADD
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