MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 871

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.6.2.3
Figure 15-122
using the 8-bit FIFO interface.
The 8-bit FIFO interface has 25 signals (including the flow control signals). Illustrative timing of the
GMII-style FIFO mode is shown in
Freescale Semiconductor
1
The flow control signals (TSEC n _CRS and TSEC n _COL) are common to all of the FIFO modes.
8-Bit GMII-Style Packet FIFO Mode
TSEC n _CRS becomes an output signal in FIFO modes only.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
depicts the signals required to establish eTSEC module connection with an external device
TX_ER/RX_ER
TX_EN/RX_DV
eTSEC
TXD/RXD[7:0]
TX/RX_CLK n
Figure 15-123. 8-Bit GMII-Style Packet FIFO Timing
Figure 15-122. eTSEC-FIFO (8-Bit) Connection
Reflected Transmit Clock (TSEC n _GTX_CLK)
Figure
Transmit Flow Control
Receive Flow Control
Receive Data Valid (TSEC n _RX_DV)
Transmit Data (TSEC n _TXD[7:0])
Transmit Enable (TSEC n _TX_EN)
Transmit Clock (TSEC n _TX_CLK)
Receive Data (TSEC n _RXD[7:0])
Receive Clock (TSEC n _RX_CLK)
SOP
Transmit Error (TSEC n _TX_ER)
Receive Error (TSEC n _RX_ER)
15-123.
1
1
(TSEC n _CRS)
(TSEC n _COL)
Enhanced Three-Speed Ethernet Controllers
EOP
with 8-Bit
Interface
ASIC
FIFO
15-139