MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 465

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11.3.1.6
The digital filter sampling rate register (I2CDFSRR) is shown in
AN2919, Determining the I
proper use of I2CFDR and I2CDFSRR.
Table 11-9
11.4
The I
or slave transmitter. After the boot sequencer has completed (when powered up in boot sequencer mode),
the I
Note that the boot sequencer only functions from the I
this purpose.
11.4.1
A standard I
Freescale Semiconductor
Bits
0–1
2–7
•
•
•
•
2
2
C interface will perform as a slave receiver.
C unit always performs as a slave receiver as a default, unless explicitly programmed to be a master
START condition
Slave target address transmission
Data transfer
STOP condition
Name
DFSR Digital filter sampling rate. To assist in filtering out signal noise, the sample rate is programmed. This field is
—
shows the field descriptions for I2CDFSRR.
Functional Description
2
Offset I
Reset
C transfer consists of the following:
Transaction Protocol
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Digital Filter Sampling Rate Register (I2CDFSRR)
Reserved
used to prescale the frequency at which the digital filter takes samples from the I
sampling rate is calculated by dividing one third the platform (CCB clock) frequency by the non-zero value of
DFSR.
W
R
I
2
2
C1: 0x014
C2: 0x114
Figure 11-7. I
0
0
2
C Frequency Divider Ratio for SCL, for additional guidance regarding the
0
1
Table 11-9. I2CDFSRR Field Descriptions
2
C Digital Filter Sampling Rate Register (I2CDFSRR)
0
2
1
2
C1 interface; the I
Description
0
DFSR
Figure
0
11-7. Refer to application note
2
C2 interface cannot be used for
Access: Read/Write
0
2
C bus. The resulting
0
7
I
2
C Interfaces
11-11