MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1056

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
EP device typically denotes a peripheral or I/O device. In RC mode, a PCI Express type 1 configuration
header is used; in EP mode, a PCI Express type 0 configuration header is used.
As an initiator, the PCI Express controller supports memory read and write operations with a maximum
transaction size of 256 bytes. In addition, configuration and I/O transactions are supported if the PCI
Express controller is in RC mode. As a target interface, the PCI Express controller accepts read and write
operations to local memory space. When configured as an EP device, the PCI Express controller accepts
configuration transactions to the internal PCI Express configuration registers. Message generation and
acceptance are supported in both RC and EP modes. Locked transactions and inbound I/O transactions are
not supported.
18.1.1.1
Outbound internal platform transactions to PCI Express are first mapped to a translation window to
determine what PCI Express transactions are to be issued. A transaction from the internal platform can
become a PCI Express Memory, I/O, Message, or Configuration transaction depending on the window
attributes.
18-2
Outbound Transactions
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Internal Platform (OCeaN) Interface
RX
RX
RX
Figure 18-1. PCI Express Controller Block Diagram
PCI Express Link
SerDes Interface
TX
TX
TX
Transaction Layer
Data Link Layer
MAC Layer
Message Manager
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