MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 709
![MPU POWERQUICC III 783-PBGA](/photos/37/62/376266/mpc8544e_image_sml.jpg)
MPC8544VTALF
Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
Specifications of MPC8544VTALF
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Company:
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Consider the following SDRAM organization:
The logical address is partitioned as shown in
The following parameters are extracted:
During the address phase, the SDRAM address port is set as shown in
Because the internal bank selects are multiplexed over LA[15:16], LSDMR[BSMA] must be set to 011.
Table 14-36
Freescale Semiconductor
msb of start address
•
•
•
•
The 32-bit port size is organized as 8 × 8 × 32 Mbits.
Each device has 4 internal banks, 13 row address lines, and 10 column address lines.
COLS = 011, 10 column lines
ROWS = 100, 13 row lines
LA[0:14]
msb of start address
shows the address port configuration during a READ/WRITE command.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 14-36. SDRAM Device Address Port During READ/WRITE Command
Table 14-33. LAD n Signal Connections to 128-Mbyte SDRAM (continued)
A[0:4]
LA[0:14]
Table 14-35. SDRAM Device Address Port During Address Phase
—
Internal bank select
LA[15:16]
LAD (Latch Address)
Table 14-34. Logical Address Bus Partitioning
LAD19 (no connect)
Internal bank select A[18:19]
A[5:17]
Row
LAD21
LAD20
LAD18
LAD17
LAD16
LAD15
LA[15:16]
LA[17:18]
Don’t care
Table
Bank select
A[18:19]
BA0 (if LSDMR[BSMA] = 011)
BA1 (if LSDMR[BSMA] = 011)
A10 is connected to LSDA10
14-34.
SDRAM Address Signal
A11
A12
Row A[5:17]
A8
A9
LA[19]
LA[17:29]
AP
A[20:29]
Column
Table
14-35.
LA[20:29]
Column
No connect
LA[30:31]
A[30:31]
lsb
Local Bus Controller
No connect
LA[30:31]
14-89
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