MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1030

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Bus Interface
asserted. Wait cycles may be inserted in a data phase by the initiator (by negating PCI_IRDY) or by the
target (by negating PCI_TRDY).
Once an initiator has asserted PCI_IRDY, it cannot change PCI_IRDY or PCI_FRAME until the current
data phase completes regardless of the state of PCI_TRDY. Once a target has asserted PCI_TRDY or
PCI_STOP, it cannot change PCI_DEVSEL, PCI_TRDY, or PCI_STOP until the current data phase
completes. In simpler terms, once an initiator or target has committed to the data transfer, it cannot change
its mind.
When the initiator intends to complete only one more data transfer (which could be immediately after the
address phase), PCI_FRAME is negated and PCI_IRDY is asserted (or kept asserted), indicating the
initiator is ready. After the target indicates the final data transfer (by asserting PCI_TRDY), the PCI bus
may return to the idle state (both PCI_FRAME and PCI_IRDY are negated) unless a fast back-to-back
transaction is in progress. In the case of a fast back-to-back transaction, an address phase immediately
follows the last data phase.
17.4.2.2
A PCI bus command is encoded in the PCI_C/BE[3:0] signals during the address phase of a PCI
transaction. The bus command indicates to the target the type of transaction the initiator is requesting.
Table 17-47
17-46
BE[3:0]
PCI_C/
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
Interrupt-
acknowledge
Special cycle
I/O-read
I/O-write
Reserved
Reserved
Memory-read
Memory-write
Reserved
Reserved
Command
PCI Bus
describes the PCI bus commands implemented by the device.
PCI Bus Commands
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
1
1
1
1
Supported
Initiator
as an
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
as a Target
Supported
Table 17-47. PCI Bus Commands
Yes
Yes
No
No
No
No
No
No
No
No
A read (implicitly addressing the system interrupt controller). Only one
device on the PCI bus should respond to this command; others ignore
it. See
more information.
Provides a way to broadcast select messages to all devices on the PCI
bus. See
information.
Accesses agents mapped into the PCI I/O space.
Accesses agents mapped into the PCI I/O space.
—
—
Accesses either local memory or agents mapped into PCI memory
space, depending on the address. When a PCI master issues this
command to local memory, the PCI controller (the target) fetches data
from the requested address to the end of the cache line (32 bytes) from
local memory, even though all of the data may not be requested by (or
sent to) the initiator.
Accesses either local memory or agents mapped into PCI memory
space, depending on the address.
—
—
Section 17.4.2.12.1, “Interrupt-Acknowledge Transactions,”
Section 17.4.2.12.2, “Special-Cycle Transactions,”
Definition
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