MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 58

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

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Transmit Deferral Packet Counter Register Definition....................................................... 15-95
Transmit Excessive Deferral Packet Counter Register Definition...................................... 15-95
Transmit Single Collision Packet Counter Register Definition .......................................... 15-96
Transmit Multiple Collision Packet Counter Register Definition....................................... 15-96
Transmit Late Collision Packet Counter Register Definition ............................................. 15-97
Transmit Excessive Collision Packet Counter Register Definition .................................... 15-97
Transmit Total Collision Counter Register Definition ........................................................ 15-98
Transmit Drop Frame Counter Register Definition ............................................................ 15-98
Transmit Jabber Frame Counter Register Definition .......................................................... 15-99
Transmit FCS Error Counter Register Definition ............................................................... 15-99
Transmit Control Frame Counter Register Definition ...................................................... 15-100
Transmit Oversized Frame Counter Register Definition .................................................. 15-100
Transmit Undersize Frame Counter Register Definition .................................................. 15-101
Transmit Fragment Counter Register Definition .............................................................. 15-101
Carry Register 1 (CAR1) Register Definition................................................................... 15-102
Carry Register 2 (CAR2) Register Definition................................................................... 15-104
Carry Mask Register 1 (CAM1) Register Definition........................................................ 15-105
Carry Mask Register 2 (CAM2) Register Definition........................................................ 15-106
Receive Filer Rejected Packet Counter Register Definition ............................................. 15-107
IGADDRn Register Definition ......................................................................................... 15-108
GADDRn Register Definition........................................................................................... 15-109
FIFOCFG Register Definition .......................................................................................... 15-110
ATTR Register Definition ................................................................................................. 15-112
ATTRELI Register Definition........................................................................................... 15-113
RQPRM Register Definition ............................................................................................. 15-114
RFBPTR0–RFBPTR7 Register Definition........................................................................ 15-114
Control Register Definition............................................................................................... 15-117
Status Register Definition ................................................................................................. 15-118
AN Advertisement Register Definition............................................................................. 15-119
AN Link Partner Base Page Ability Register Definition .................................................. 15-121
AN Expansion Register Definition ................................................................................... 15-122
AN Next Page Transmit Register Definition .................................................................... 15-123
AN Link Partner Ability Next Page Register Definition .................................................. 15-124
Extended Status Register Definition ................................................................................. 15-124
Jitter Diagnostics Register Definition ............................................................................... 15-125
TBI Control Register Definition ....................................................................................... 15-126
eTSEC-MII Connection .................................................................................................... 15-128
eTSEC-RMII Connection ................................................................................................. 15-129
eTSEC-RGMII Connection............................................................................................... 15-130
eTSEC-TBI Connection .................................................................................................... 15-131
eTSEC-RTBI Connection ................................................................................................. 15-132
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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