MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 326

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DDR Memory Controller
9.2
The DDR memory controller includes these distinctive features:
9-2
•
•
•
•
•
•
•
•
•
Request from
Address from
management
Support for DDR2 and DDR SDRAM
64-/72-bit SDRAM data bus. 32-/40-bit SDRAM for DDR and DDR2
Programmable settings for meeting all SDRAM timing parameters
The following SDRAM configurations are supported:
— As many as four physical banks (chip selects), each bank independently addressable
— 64-Mbit to 4-Gbit devices depending on internal device configuration with x8/x16/x32 data
— Unbuffered and registered DIMMs
Chip select interleaving support
Support for data mask signals and read-modify-write for sub-double-word writes. Note that a
read-modify-write sequence is only necessary when ECC is enabled.
Support for double-bit error detection and single-bit error correction ECC (8-bit check word across
64-bit data)
Open page management (dedicated entry for each logical bank)
Automatic DRAM initialization sequence or software-controlled initialization sequence
Data from
Data from
Features
ECM
SDRAM
To error
ports (no direct x4 support)
master
master
master
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figure 9-1. DDR Memory Controller Simplified Block Diagram
Signals
Address
Decode
Error
RMW
ECC
Open
Table
Row
ECC
FIFO
SDRAM
Control
Delay chain
Address
SDRAM
Control
Control
Control
Clock
EN
EN
Freescale Semiconductor
DDR SDRAM
Memory Array
DDR SDRAM
Memory Control
Data Qualifiers
Data Signals
Clocks
MA[15:0]
MCKE[0:3]
MBA[2:0]
MCS[0:3]
MCAS
MRAS
MWE
MDM[0:8]
MODT[0:3]
MDIC[0:1]
MDQS[0:8]
MDQ[0:63]
MECC[0:7]
MCK[0:5]
MCK[0:5]
MDQS[0:8]