MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1264

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Revision History
15.4.1/15-8
15.5.1/15-13
15.5.2/15-14
15.5.3.2.3/15-43
15.5.3.3.1/15-49
15.5.3.3.8/15-59
15.5.3.5.2/15-69
15.5.3.6.26/15-93
15.5.3.9.2/15-112
15.5.3.10/15-113
15.6.3.8/15-151
15.6.4.3/15-160
15.6.6/15-170
15.6.7.3/15-177
17.1.1.2/17-4
17.2/17-6
18.3.8.1.2/18-44
A-2
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
In
“This input is not used in MII, RMII, or FIFO modes.
to:
“This input is not used in SGMII, MII, RMII, or FIFO modes.
Also, changed TSECn_TX_EN signal description from “rising and falling edges
of the TSECn_TX_CLK, respectively.”
to
“rising and falling edges of the TSECn_GTX_CLK, respectively.”
In
In
Changed the fourth sentence in DFVLAN introductory text from:
“Frames with an Ethertype of 0x8808 will be dropped by the receiver unless
RCNTRL[CFA] is set.”
to
“Frames with an Ethertype of 0x8808 will be dropped by the receiver.”
In
addition, clarified the bit field description of RSF.
In
parser/filer behavior with ethertype field (parsed into ETY).
Also, added text to the bit field description of IPF.
In
be from 0x3 to 0xF.
In
In
EI.
Added
subsections.
Clarified last sentence of the section to include multicast packets.
In
Added
In
updated to include a recommendation to use 64-byte aligned receive buffer pointer
addresses.
Added a note to the first paragraph, stating that inbound writes less than 4-bytes
are split into single bytes writes to the target.
In
In
Figure 15-104
Table
Table
Table
Figure 15-22
Table
Table
Table
Table 15-140,
Table
Table
Table
Section 15.5.3.10, “Lossless Flow Control Configuration Registers,”
Section 15.6.6, “Lossless Flow Control,”
15-2, changed the description of EC_GTX_CLK125 from:
15-3, added a row for the lossless flow control registers.
15-4, added a section of lossless flow control registers.
15-33, clarified the bit field description of ETY with a description of
15-40, clarified that the bit field description of “Preamble Length” may
15-80, changed bit field TPKT to 22 bits (bits 10–31).
15-147, bit field description of “Rx Data Buffer Pointer” has been
17-2, added PCI_CLK.
18-36, corrected the device ID description.
and
added text to bit field descriptions of IP and PRO.
and
Table
Table
15-26, added bit 17, LFC (lossless flow control). In
15-107, corrected the size and bit field description of
and subsections.
Freescale Semiconductor
and