MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1080

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Express Interface Controller
Table 18-19
18.3.5.2.4
The PCI Express inbound window base address registers, shown in
for the windows which are translated to an alternate target address space. In root complex (RC) mode,
addresses for inbound transactions are compared to these windows. In RC mode, PEXIWBAR0 is located
in the PCI Express type 1 configuration header space and PEXIWBAR[1–3] registers are implemented as
described in this section. In endpoint (EP) mode, these registers are not implemented in the
memory-mapped space. Reading these registers in EP mode will return all zeros and writing to these
offsets has no consequences. All base address registers in EP are located in the PCI Express type 0
configuration header space. Note that PEXIWBAR1 only supports 32-bit PCI Express address space.
Table 18-20
18-26
12–31
12–31
8–11
0–11
Bits
Bits
0–7
Offset Window 1: 0xDE8
Reset
WBEA Window base extended address. This field corresponds to PCI Express address bits [43:32]. Note that the
Name
Name
WBA
TEA
TA
—
Table 18-20. PCI Express Inbound Window Base Address Register Field Descriptions
Table 18-19. PCI Express Inbound Translation Address Registers Field Descriptions
W
Figure 18-21. PCI Express Inbound Window Base Address Registers (PEXIWBAR n )
R
describes the fields of the PCI Express inbound translation address registers.
describes the fields of the PCI Express inbound window base address registers.
Window 2: 0xDC8
Window 3: 0xDA8
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
PCI Express Inbound Window Base Address Registers (PEXIWBAR n )
Reserved
Translation extended address. Target address which indicates the starting point of the inbound translated
address. The translation address must be aligned based on the size field. Corresponds to internal platform
address bits [0:3] where bit 0 is the msb of the internal platform address.
Translation address. Target address which indicates the starting point of the inbound translated address. The
translation address must be aligned based on the size field. This corresponds to internal platform address
bits [4:23].
extended address is supported for windows 2 and 3 only; for PEXIWBAR1, these bits are reserved and must
be 0.
Window base address. Source address which is the starting point for the inbound translation window. The
window must be aligned based on the size selected in the window size bits. This corresponds to PCI Express
address bits [31:12].
(Windows 2 and 3 only)
WBEA
11 12
All zeros
Description
Description
Figure
WBA
18-21, select the base address
Access: Read/Write
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