MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 219

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Chapter 6
Core Register Summary
This chapter describes the e500 register model and indicates whether each register is defined by the Power
Architecture technology, by the Freescale embedded category implementation standards (EIS), or by the
implementation. For the programmer, drawing this distinction indicates the degree to which code is
portable among Freescale processors.
This chapter provides reference material—figures for each register and complete descriptions of register
fields, including how the registers are accessed, reset values, and whether they can be accessed by user-
and supervisor-level software. Detailed discussions of how these registers are used are provided in EREF:
A Reference for Freescale Book E and the e500 Core and the PowerPC™ e500 Core Family Reference
Manual.
Note that all registers described here are implemented in the hardware as part of the e500 core.
6.1
Overview
As shown in
Figure
6-1, most of the registers implemented are defined by the architecture, and most of
those were defined by the AIM definition of the architecture and have changed very little. Additional
registers and fields within registers are defined by the EIS and by the implementation.
The Power Architecture technology defines some register fields in a very general way, leaving some
details as implementation specific. In some cases, this more specific functionality is defined by the EIS;
in others it is left up to the processor. This chapter identifies the level at which each features is defined.
References to e500 are true for both the e500v1 and e500v2.
6.1.1
Register Set
Table 6-1
shows the e500 register set, grouped by whether they can be accessed by user- or
supervisor-level software. Unless otherwise indicated, these registers are defined by the base or embedded
category.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor
6-1