MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 724

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Local Bus Controller
Figure 14-84
HCID on the first falling edge of the host read strobe signal (HRDS) on which the HCS is asserted. If
HCID[0:3] match the CHIPID value, the DSI is accessed. When the DCR[8]:RPE bit is set, read access to
the memory space (not to the register space) initiates data prefetching from consecutive addresses in the
internal memory space. The DSI signals (with the assertion of the host transfer acknowledge signal (HTA))
that data is valid, and the host can sample the host data bus (HD) and terminate the access by negating
HRDS. If the data for this access is already in the read buffer due to the prefetch mechanism, assertion time
of HTA is improved. The WAEN feature of the UPM must be used to insert wait states while the DSI is
busy. MxMR[UWPL] has to be cleared to interpret the correct polarity of the HTA signal.
Because the UPM is used in the mode, the DCR[4]:HTAAD should be set to 1 and the drive time control
field, DCR[9–10]:HTADT, should be defined to a value different than 00. This mode is specially designed
to be used for implementations with a pull-up resistor on HTA.
The host can start its next access (back-to-back accesses) without negating the HCS signal between
accesses. If the next access is not to the same MSC8102, then to prevent contention on HTA, the host must
wait until the previous DSI stops driving HTA before it accesses the next device. If the next access is to
the same MSC8102, the host must not start consecutive access before HTA is actively driven to 1 by the
previous access. The easiest way to achieve this is to insert idle cycles at the end of the UPM pattern to
guarantee that HTA is inactive.
14-104
HWBS[0:7]
HDST[0:1]
HA[11:29]
HCID[0:3]
HD[0:63]
shows an asynchronous read access. The DSI samples the host address bus (HA
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
HRDS
HCS
HTA
Legend:
Timing conventions:
1
0
1
0
Figure 14-83. Asynchronous Write to MSC8102 DSI
Valid value that can be 1 or 0
Don’t care
Three-state output signal that is not driven by the DSI
HTAAD=1 & HTADT = 01,10,11
HTAAD = 0 & HTADT = 00
Freescale Semiconductor
)
and the