MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 306

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM
7-36
icbtls_L2
Cache-inhibited instruction
fetch
Cacheable load (4-state)
Cacheable lwarx (4-state)
dcbt_L1 (4-state)
dcbtls_L1 (4-state)
Cache-inhibited load
Cache-inhibited lwarx
Writeback Store
Writeback stwcx
Cacheable load (3-state)
Cacheable lwarx (3-state)
dcbt_L1 (3-state)
dcbtls_L1 (3-state)
dcbt_L2
dcbtst_L2
dcbtst_L1
dcbtstls_L1
Source of Transaction
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 7-27. State Transitions Due to Core-Initiated Transactions (continued)
Initial States
dL1
N/A
dL1
N/A
N/A
dL1
dL1
dL1
dL1
dL1
I,E
I,E
L1
I
I
I
I
I
E/EL
E/EL
N/A
N/A
N/A
EL
EL
EL
EL
EL
EL
EL
L2
I/T
I/T
I/T
I/T
I/T
E
E
T
E
T
E
E
T
E
T
E
I
I
I
I
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Hit
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
L2
Final States
N/A
N/A
N/A
EL
E/I
E/I
E/I
E/I
E/I
E/I
E/I
L1
M
M
M
M
M
M
E
E
E
E
E
E
E
E
I
I
I
I
I
I
I
same L2CTL[L2DO] = 1
same L2CTL[L2DO] = 0
same L2CTL[L2IO] = 1
same L2CTL[L2IO] = 0
same L2 allocates when a line is cast out of L1.
same
same L2CTL[L2IO] = 0
same
N/A
N/A
N/A
EL
EL
EL
EL
EL
L2
T
T
E
T
T
T
T
E
T
I
I
I
I
I
I
I
L2CTL[L2DO] = 1
L2CTL[L2DO] = 1
L2CTL[L2DO] = 0
L2CTL[L2DO] = 0
L2CTL[L2DO] = 0. Restore locked line in L2 with
valid data from bus
No L1/L2 effect
L2CTL[L2IO] = 1
L2CTL[L2IO] = 1
L2CTL[L2IO] = 0
L2CTL[L2IO] = 0. Restore locked line in L2 with
valid data from bus
No L1/L2 effect
No L2 effect
L2CTL[L2IO] = 1
L2CTL[L2IO] = 1
L2CTL[L2IO] = 1
L2CTL[L2IO] = 1
L2CTL[L2IO] = 0
L2CTL[L2IO] = 0. Restore locked line with valid
data from bus
Comments
Freescale Semiconductor