MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 33

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Paragraph
Number
16.3.1.4
16.3.1.5
16.3.1.6
16.3.1.7
16.3.1.8
16.3.1.9
16.3.1.10
16.3.1.11
16.3.1.12
16.3.1.13
16.3.1.14
16.4
16.4.1
16.4.1.1
16.4.1.1.1
16.4.1.1.2
16.4.1.1.3
16.4.1.1.4
16.4.1.2
16.4.1.2.1
16.4.1.2.2
16.4.1.2.3
16.4.1.2.4
16.4.1.3
16.4.1.4
16.4.1.4.1
16.4.1.4.2
16.4.1.5
16.4.1.6
16.4.1.7
16.4.1.8
16.4.2
16.4.3
16.4.4
16.4.5
16.5
16.5.1
16.5.1.1
Freescale Semiconductor
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Functional Description................................................................................................. 16-25
DMA System Considerations ...................................................................................... 16-38
DMA Channel Operation......................................................................................... 16-25
DMA Transfer Interfaces ......................................................................................... 16-33
DMA Errors ............................................................................................................. 16-33
DMA Descriptors..................................................................................................... 16-34
Limitations and Restrictions .................................................................................... 16-37
Unusual DMA Scenarios ......................................................................................... 16-40
Source Attributes Registers (SATRn).................................................................. 16-15
Source Address Registers (SARn)....................................................................... 16-16
Destination Attributes Registers (DATRn).......................................................... 16-17
Destination Address Registers (DARn)............................................................... 16-18
Byte Count Registers (BCRn) ............................................................................. 16-19
Next Link Descriptor Address Registers
Current List Descriptor Address Registers
Next List Descriptor Address Registers
Source Stride Registers (SSRn) ........................................................................... 16-22
Destination Stride Registers (DSRn) ................................................................... 16-23
DMA General Status Register (DGSR) ............................................................... 16-24
Basic DMA Mode Transfer ................................................................................. 16-26
Extended DMA Mode Transfer ........................................................................... 16-28
External Control Mode Transfer.......................................................................... 16-30
Channel Continue Mode for Cascading Transfer Chains .................................... 16-31
Channel Abort...................................................................................................... 16-32
Bandwidth Control............................................................................................... 16-32
Channel State ....................................................................................................... 16-32
Illustration of Stride Size and Stride Distance..................................................... 16-33
DMA to e500 Core .............................................................................................. 16-40
(NLNDARn and ENLNDARn) ....................................................................... 16-19
(CLSDARn and ECLSDARn)......................................................................... 16-21
(NLSDARn and ENLSDARn) ........................................................................ 16-22
Basic Direct Mode ........................................................................................... 16-26
Basic Direct Single-Write Start Mode ............................................................. 16-26
Basic Chaining Mode ...................................................................................... 16-27
Basic Chaining Single-Write Start Mode ........................................................ 16-28
Extended Direct Mode..................................................................................... 16-28
Extended Direct Single-Write Start Mode....................................................... 16-28
Extended Chaining Mode ................................................................................ 16-29
Extended Chaining Single-Write Start Mode .................................................. 16-29
Basic Mode ...................................................................................................... 16-31
Extended Mode................................................................................................ 16-32
Contents
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