MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 739

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 15-1
Freescale Semiconductor
TSEC n _GTX_CLK
EC_GTX_CLK125
TSEC n _RXD[7:4]
TSEC n _RXD[3:0]
TSEC n _RX_CLK
TSEC n _RX_DV
TSEC n _RX_ER
Signal Name
TSEC n _COL
TSEC n _CRS
EC_MDIO
EC_MDC
lists the network interface signals.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MII—collision, input
FIFO—transmit flow control, input
MII—carrier sense, input
TBI—signal detect, input
FIFO—receive flow control, output
RTBI, RGMII—inverted transmit clock feedback, output
TBI
FIFO—continuous transmit clock feedback, output
GMII, MII, RMII—transmit clock feedback when transmission is enabled, zero otherwise,
output
Oscillator source for GMII, TBI, RGMII, RTBI transmit clock, input, shared by eTSEC1 and
eTSEC3
TBI, RTBI, GMII, RGMII, MII, RMII—Management clock, output.
TBI, RTBI, GMII, RGMII, MII, RMII—Management data, bidirectional.
GMII, MII, RGMII—receive clock, input
TBI—PMA receive clock 0, input
FIFO—receive clock, input
GMII, MII—receive data valid, input
TBI—receive code group (RCG) bit 8, input
RGMII (RX_CLK rising)—receive data valid, input
RGMII (RX_CLK falling)—receive error, input
RTBI (RX_CLK rising)—receive code group (RCG) bit 4, input
RTBI (RX_CLK falling)—receive code group (RCG) bit 9, input
RMII—CRS_DV carrier sense/data valid, input
FIFO—receive data valid or receive control bit, input
GMII—receive data bits 7:4 input
TBI—RCG bits 7:4, input
FIFO—receive data bits 7:4 input
MII, RGMII, RTBI, RMII—unused
GMII, MII—Receive data bits 3:0, input
TBI—RGC bits 3:0, input
RGMII (RX_CLK rising) —Receive data bits 3:0, input
RGMII (RX_CLK falling)—Receive data bits 7:4, input
RTBI (RX_CLK rising)—RCG bits 3:0, input
RTBI (RX_CLK falling)—RCG bits 8:5, input
RMII—RXD[1:0] receive data bits, input
RMII—RXD[3:2] are unused
FIFO—Receive data bits 3:0, input
GMII, MII, RMII—Receive error, input
TBI—RGC bit 9, input
FIFO—Receive error or receive frame control bit, input
RGMII, RTBI—Unused, output driven zero
Table 15-1. eTSEC n Network Interface Signal Properties
Function
Enhanced Three-Speed Ethernet Controllers
Hi-Z (input)
Reset
State
—
—
—
—
—
—
—
—
0
0
15-7