MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 767

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 15-12
15.5.3.1.8
DMACTRL is writable by the user to configure the DMA block.
the DMACTRL register.
Table 15-13
Freescale Semiconductor
Offset eTSEC1:0x2_402C; eTSEC3:0x2_502C
Reset
17–23
16–31
0–15
Bits
0–15
Bits
16
24
25
26
W
R
0
TBDSEN TxBD snoop enable.
TDSEN Tx Data snoop enable.
Name
Name
PTE
LE
—
—
—
PT
describes the fields of the PTV register.
describes the fields of the DMACTRL register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
DMA Control Register (DMACTRL)
Extended pause control. This field allows software to add a 16-bit additional control parameter into the PAUSE
frame to be sent when TCTRL[TFC_PAUSE] is set. Note that current IEEE 802.3 PAUSE frame format
requires this parameter to be cleared.
Pause time value. Represents the 16-bit pause quanta (i.e. 512 bit times). This pause value is used as part
of the PAUSE frame to be sent when TCTRL[TFC_PAUSE] is set. See
page 15-151
Reserved
Little-endian descriptor mode enable. This bit controls both the reading and writing of descriptors; data
buffers are always transferred in network byte order.
0 RxBDs and TxBDs are interpreted with big-endian byte ordering, as shown in
1 RxBDs and TxBDs are interpreted with little-endian byte ordering. That is, the 16 bits of flags are
Reserved
0 Disables snooping of all transmit frames from memory.
1 Enables snooping of all transmit frames from memory.
0 Disables snooping of all transmit BD memory accesses.
1 Enables snooping of all transmit BD memory accesses.
Reserved
Buffer Descriptors.”
considered a complete half-word unit, the buffer length is considered another complete half-word unit, and
the buffer pointer is considered a complete word unit.
—
for more information.
Table 15-13. DMACTRL Field Descriptions
Table 15-12. PTV Field Descriptions
Figure 15-9. DMACTRL Register
15 16 17
LE
—
All zeros
Description
Description
23
TDSEN TBDSEN — GRS GTS TOD WWR WOP
24
Figure 15-9
Enhanced Three-Speed Ethernet Controllers
25
Section 15.6.3.9, “Flow Control,” on
26
describes the definition for
27
Section 15.6.7.1, “Data
28
Access: Read/Write
29
30
15-35
31