MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 47

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure
Number
6-40
6-41
6-42
6-43
6-44
6-45
6-46
6-47
6-48
6-49
6-50
6-51
6-52
6-53
6-54
6-55
6-56
6-57
6-58
6-59
6-60
6-61
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
Freescale Semiconductor
MMU Configuration Register (MMUCFG) ......................................................................... 6-32
TLB Configuration Register 0 (TLB0CFG) ......................................................................... 6-33
TLB Configuration Register 1 (TLB1CFG) ......................................................................... 6-34
MAS Register 0 (MAS0) ...................................................................................................... 6-35
MAS Register 1 (MAS1) ...................................................................................................... 6-35
MAS Register 2 (MAS2) ...................................................................................................... 6-36
MAS Register 3 (MAS3) ...................................................................................................... 6-37
MAS Register 4 (MAS4) ...................................................................................................... 6-38
MAS Register 6 (MAS6) ...................................................................................................... 6-38
MAS Register 7 (MAS7) ...................................................................................................... 6-39
Debug Control Register 0 (DBCR0) ..................................................................................... 6-39
Debug Control Register 1 (DBCR1) ..................................................................................... 6-41
Debug Control Register 2 (DBCR2) ..................................................................................... 6-42
Debug Status Register (DBSR)............................................................................................. 6-43
Instruction Address Compare Registers (IAC1–IAC2) ........................................................ 6-45
Data Address Compare Registers (DAC1–DAC2) ............................................................... 6-45
Signal Processing and Embedded Floating-Point Status and
Accumulator (ACC) .............................................................................................................. 6-47
Performance Monitor Global Control Register 0 (PMGC0),
Local Control A Registers (PMLCa0–PMLCa3), User Local Control A Registers
Local Control B Registers (PMLCb0–PMLCb3)/User Local Control B Registers
Performance Monitor Counter Registers (PMC0–PMC3)/User Performance Monitor
L2 Cache/SRAM Configuration ............................................................................................. 7-1
Cache Organization ................................................................................................................. 7-4
Physical Address Usage for L2 Cache Accesses .................................................................... 7-5
Physical Address Usage for SRAM Accesses ........................................................................ 7-6
Data Bus Connection of CCB ................................................................................................. 7-8
Address Bus Connection of CCB............................................................................................ 7-8
L2 Control Register (L2CTL) ............................................................................................... 7-10
Cache External Write Address Registers (L2CEWARn) ...................................................... 7-13
Cache External Write Address Registers Extended Address (L2CEWAREAn)................... 7-14
Cache External Write Control Registers (L2CEWCR0–L2CEWCR3) ................................ 7-14
L2 Memory-Mapped SRAM Base Address Registers (L2SRBARn)................................... 7-16
L2 Memory-Mapped SRAM Base Address Registers Extended Address 0–1
L2 Error Injection Mask High Register (L2ERRINJHI) ...................................................... 7-18
Control Register (SPEFSCR) ........................................................................................... 6-45
User Performance Monitor Global Control Register 0 (UPMGC0) ................................ 6-49
(UPMLCa0–UPMLCa3) .................................................................................................. 6-50
(UPMLCb0–UPMLCb3).................................................................................................. 6-51
Counter Registers (UPMC0–UPMC3)............................................................................. 6-52
(L2SRBAREAn) .............................................................................................................. 7-17
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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