MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1151

MPU POWERQUICC III 783-PBGA

MPC8544VTALF

Manufacturer Part Number
MPC8544VTALF
Description
MPU POWERQUICC III 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8544VTALF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
667MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Processor Series
MPC85xx
Core
e500
Data Bus Width
32 bit
Maximum Clock Frequency
667 MHz
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
Data Ram Size
32 KB
I/o Voltage
1.8 V, 3.3 V
Interface Type
I2C, HSSI, DUART
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8544VTALF
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC8544VTALFA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
PCI Express Interface Controller
18.4
Functional Description
The PCI Express protocol relies on a requestor/completer relationship where one device requests that some
desired action be performed by some target device and the target device completes the task and responds.
Usually the requests and responses occur through a network of links, but to the requestor and to the
completer, the intermediate components are transparent.
Intermediate
Ultimate
Requestor
Link
Link
Component(s)
Completer
Figure 18-122. Requestor/Completer Relationship
Each PCI device is divided into two halves-transmit (TX) and receive (RX), and each of these halves is
further divided into three layers—transaction, data link, and physical—as shown in
Figure
18-123.
Transaction
Transaction
Data Link
Data Link
Physical
Physical
Logical Sub-block
Logical Sub-block
Electrical Sub-block
Electrical Sub-block
RX
TX
RX
TX
Figure 18-123. PCI Express High-Level Layering
Packets are formed in the transaction layer (TLPs) and data link layer (DLLPs), and each subsequent layer
adds the necessary encodings and framing—as shown in
Figure
18-124. As packets are received, they are
decoded and processed by the same layers but in reverse order, so they may be processed by the layer or
by the device application software.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor
18-97

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