MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 175

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.4.3.8
The boot sequencer configuration options, shown in
configuration data from the serial ROM located on the I
MPC8544E. These options also specify normal or extended I
“Boot Sequencer Mode,”
Note that the values latched on these signals during POR are accessible through the memory-mapped
PORBMSR (POR boot mode status register) described in
Register (PORBMSR).”
Freescale Semiconductor
LGPL3/LSDCAS,
Functional
Default (1)
Default (11)
Functional
Signal
LA27
Signal
LGPL5
Boot Sequencer Configuration
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reset Configuration
When the boot sequencer is enabled, the processor core will be held in reset
and thus prevented from fetching boot code until the boot sequencer has
completed its task, regardless of the state of the CPU boot configuration
signal described in
Reset Configuration
cfg_cpu_boot
cfg_boot_seq[0:1]
Name
Name
for more information on the boot sequencer.
Table 4-16. Boot Sequencer Configuration
Section 4.4.3.7, “CPU Boot
Table 4-15. CPU Boot Configuration
(Binary)
Value
(Binary)
Value
0
1
00
01
10
11
CPU boot holdoff mode. The e500 core is prevented from booting until
configured by an external master.
The e500 core is allowed to boot without waiting for configuration by an
external master (default).
Reserved
Normal I
loads configuration information from a ROM on the I
ROM must be present.
Extended I
loads configuration information from a ROM on the I
ROM must be present.
Boot sequencer is disabled. No I
NOTE
2
Table
C addressing mode is used. Boot sequencer is enabled and
2
C addressing mode is used. Boot sequencer is enabled and
2
C1 port before the host tries to configure the
Section 19.4.1.2, “POR Boot Mode Status
4-16, allow the boot sequencer to load
2
C addressing modes. See
Configuration.”
Meaning
Meaning
2
C ROM is accessed (default).
Reset, Clocking, and Initialization
2
Section 11.4.5,
2
C1 interface. A valid
C interface. A valid
4-17