MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 1219

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Freescale Semiconductor
Channel 1 read DW or less
Channel 2 read DW or less
Channel 3 read DW or less
Channel 0 write DW or less
Channel 1 write DW or less
Channel 2 write DW or less
Channel 3 write DW or less
ECM request wait core
ECM request wait I
ECM request wait PCI//DMA
ECM request wait eTSEC1
ECM request wait eTSEC3
ECM dispatch
ECM dispatch from core
ECM dispatch from eTSEC1
ECM dispatch from eTSEC3
ECM dispatch from PCI
ECM dispatch from PEX2
ECM dispatch from PEX1
ECM dispatch from PEX3
ECM dispatch from DMA
ECM dispatch from Security
ECM dispatch from other
ECM dispatch to DDR
ECM dispatch to L2
ECM dispatch to SRAM
ECM dispatch to LBC
ECM dispatch to PCI
ECM dispatch to PEX2
ECM dispatch to PEX1
ECM dispatch to PEX3
Event Counted
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
C/Security
Table 20-10. Performance Monitor Events (continued)
C2:71 and C6:122 DMA channel 1 read double word valid
C3:70 and C7:118 DMA channel 2 read double word valid
C4:72 and C8:116 DMA channel 3 read double word valid
e500 Coherency Module (ECM) Events
Number
C2:105
Ref:15
C1:69
C2:72
C3:71
C4:73
C8:77
C7:77
C5:80
C6:80
C4:84
C1:80
C3:83
C8:80
C6:81
C7:80
C8:81
C7:94
C7:78
C9:81
C8:78
C4:86
C5:82
C1:79
C6:82
C8:79
C9:83
C1:85
DMA channel 0 write double word valid
DMA channel 1 write double word valid
DMA channel 2 write double word valid
DMA channel 3 write double word valid
Asserted for every cycle core request occurs
Asserted for every cycle I2C/Security request occurs
Asserted for every cycle PCI/PEX/DMA request occurs
Asserted for every cycle eTSEC1 request occurs
Asserted for every cycle eTSEC3 request occurs
ECM dispatch (includes address only’s)
Note: All ECM dispatch events are for committed dispatches
ECM dispatch from core (includes address only’s)
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Description of Event Counted
Device Performance Monitor
20-19