MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 722

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Local Bus Controller
Rather than restrict the firmware to avoid consecutive bus accesses to host port registers, the negation hold
off times should be accommodated in the UPM hardware interface settings. Additional clocks must be
built into the end of UPM based cycle giving appropriate time before the next bus cycle starts.
The timings can be readily adapted to allow external decode logic to be added to support chip selects for
a larger number of DSP HDI16 host ports.
14.5.6.2
The MSC8102 direct-slave interface (DSI) gives an external host direct access to the MSC8102. It
provides the following slave interfaces to an external host:
The DSI supports a 32- or 64-bit data bus. For connection to the local bus the DSI has to be configured in
32-bit mode. This is achieved through the DSP reset configuration.
The DSI supports two addressing modes, which are determined during the MSC8102 boot sequence. Refer
to details in the MSC8102 documentation.
14.5.6.2.1
The local bus supports the DSI single strobe as well as the DSI double strobes of operation. As an example
the dual strobe configuration is shown below.
14-102
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Asynchronous SRAM-like interface giving the host single accesses (with no external clock).
Synchronous SSRAM-like interface giving the host single or burst accesses of 256 bits (eight beats
of 32 bits or four beats of 64 bits) with its external clock decoupled from the MSC8102 internal
bus clock.
Full address bus mode with HA[11:29] used in both 32-bit data mode and 64-bit data mode
Sliding window mode with HA[14:29] used in both 32-bit data mode and 64-bit data mode
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Interfacing to MSC8102 DSI
DSI in Asynchronous SRAM-Like Mode
Freescale Semiconductor