MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 990

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PCI Bus Interface
17.2
Figure 17-2
Table 17-2
17-6
PCI_AD[31:0]
Signal
External Signal Descriptions
contains the detailed descriptions of the external PCI interface signals.
shows the external PCI signals.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O
I/O PCI address/data bus. The PCI address/data bus consists of signals that are both input and output
O As outputs for the bidirectional PCI address/data bus, these signals operate as described below.
I As inputs for the bidirectional PCI address/data bus, these signals operate as described below.
Table 17-2. PCI Interface Signals—Detailed Signal Descriptions
signals on this PCI controller.
Meaning
Meaning
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Arbitration
Command
Reporting
State
State
and Data
Interface
Address
37 signals
10 signals
6 signals
2 signals
Error
Asserted/Negated—Represents the physical address during the address phase of a PCI
Asserted/Negated—Represents the address to be decoded as a check for device select
Figure 17-2. PCI Interface External Signals
transaction. During the data phase(s) of a PCI transaction, the PCI address/data bus
contain the data being written.
The PCI_AD[7:0] signals define the LSB and PCI_AD[31:24] the MSB.
during the address phase of a PCI transaction or the data being received during the
data phase(s) of a PCI transaction.
The PCI_AD[7:0] signals define the LSB and PCI_AD[31:24] the MSB.
PCI_AD[31:0]
PCI_C/BE[3:0]
PCI_PAR
PCI_FRAME
PCI_TRDY
PCI_IRDY
PCI_STOP
PCI_DEVSEL
PCI_IDSEL
PCI_PERR
PCI_SERR
PCI_REQ[4:0]
PCI_GNT[4:0]
PCI_CLK
Description
32
4
1
1
1
1
1
1
1
1
1
5
5
1
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