MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 468

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

I
11.4.1.5
The following sections give details of how aspects of the protocol are implemented in this I
11.4.1.5.1
The different conditions of the I
11.4.1.5.2
The I
of the I
The SDA output can only change at the midpoint of a low cycle of the SCL, unless it is performing a
START, STOP, or restart condition. Otherwise, the SDA output is held constant.
The SDA signal is pulled low when one or more of the following conditions are true in either master or
slave mode:
The SCL signal corresponds to the internal SCL signal when one or more of the following conditions are
true in either master or slave mode:
11-14
2
C Interfaces
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•
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•
•
•
•
2
C module contains logic that controls the output to the serial data (SDA) and serial clock (SCL) lines
2
START conditions are detected when an SDA fall occurs while SCL is high.
STOP conditions are detected when an SDA rise occurs while SCL is high.
Data transfers in progress are canceled when a STOP condition is detected or if there is a slave address
mismatch. Cancellation of data transactions resets the clock module.
The bus is detected to be busy upon the detection of a START condition, and idle upon the detection
of a STOP condition.
Master mode
— Data bit (transmit)
— Ack bit (receive)
— START condition
— STOP condition
— Restart condition
Slave mode
— Acknowledging address match
— Data bit (transmit)
— Ack bit (receive)
Master mode
— Bus owner
— Lost arbitration
— START condition
— STOP condition
— Restart condition begin
— Restart condition end
C. The SCL output is pulled low as determined by the internal clock generated in the clock module.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Protocol Implementation Details
Transaction Monitoring—Implementation Details
Control Transfer—Implementation Details
2
C data transfers are monitored as follows:
Freescale Semiconductor
2
C module.