MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 17

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Paragraph
Number
10.3.8.2
10.3.8.3
10.3.8.4
10.3.8.5
10.4
10.4.1
10.4.1.1
10.4.1.2
10.4.1.3
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
10.4.7
10.4.8
10.5
10.5.1
10.5.1.1
10.5.1.2
11.1
11.1.1
11.1.2
11.1.3
11.2
11.2.1
11.2.2
11.3
11.3.1
11.3.1.1
11.3.1.2
11.3.1.3
11.3.1.4
11.3.1.5
11.3.1.6
11.4
11.4.1
Freescale Semiconductor
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Functional Description................................................................................................. 10-48
Initialization/Application Information ......................................................................... 10-53
Introduction.................................................................................................................... 11-1
External Signal Descriptions ......................................................................................... 11-3
Memory Map/Register Definition ................................................................................. 11-4
Functional Description..................................................................................................11-11
Flow of Interrupt Control......................................................................................... 10-48
Nesting of Interrupts ................................................................................................ 10-51
Spurious Vector Generation ..................................................................................... 10-51
Messaging Interrupts................................................................................................ 10-51
Shared Message Signaled Interrupts........................................................................ 10-51
PCI Express INTx.................................................................................................... 10-52
Global Timers .......................................................................................................... 10-52
Reset of the PIC ....................................................................................................... 10-53
Programming Guidelines ......................................................................................... 10-53
Overview.................................................................................................................... 11-2
Features...................................................................................................................... 11-2
Modes of Operation ................................................................................................... 11-2
Signal Overview ........................................................................................................ 11-3
Detailed Signal Descriptions ..................................................................................... 11-3
Register Descriptions................................................................................................. 11-5
Transaction Protocol .................................................................................................11-11
Processor Current Task Priority Register (CTPR)............................................... 10-46
Who Am I Register (WHOAMI) ......................................................................... 10-47
Processor Interrupt Acknowledge Register (IACK)............................................ 10-47
Processor End of Interrupt Register (EOI) .......................................................... 10-48
Interrupt Source Priority ...................................................................................... 10-50
Processor Current Task Priority........................................................................... 10-50
Interrupt Acknowledge ........................................................................................ 10-50
PIC Registers ....................................................................................................... 10-54
Changing Interrupt Source Configuration ........................................................... 10-55
I
I
I
I
I
Digital Filter Sampling Rate Register (I2CDFSRR) ............................................11-11
2
2
2
2
2
C Address Register (I2CADR) ........................................................................... 11-6
C Frequency Divider Register (I2CFDR)........................................................... 11-6
C Control Register (I2CCR) ............................................................................... 11-7
C Status Register (I2CSR) .................................................................................. 11-9
C Data Register (I2CDR).................................................................................. 11-10
Contents
I
2
Chapter 11
C Interfaces
Title
Number
Page
xvii