MPC8544VTALF Freescale Semiconductor, MPC8544VTALF Datasheet - Page 327

• Manufacturer Part Number: MPC8544VTALF
• Description: MPU POWERQUICC III 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8544VTALF

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Data Ram Size: 32 KB
• I/o Voltage: 1.8 V, 3.3 V
• Interface Type: I2C, HSSI, DUART
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

9.2.1
The DDR memory controller supports the following modes:
9.3
This section provides descriptions of the DDR memory controller’s external signals. It describes each
signal’s behavior when the signal is asserted or negated and when the signal is an input or an output.
9.3.1
Memory controller signals are grouped as follows:
Table 9-1
specification has a pinout diagram showing pin numbers. It also lists all electrical and mechanical
specifications.
Freescale Semiconductor
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Automatic DRAM data initialization
Support for up to eight posted refreshes
Memory controller clock frequency of two times the SDRAM clock with support for sleep power
management
Support for error injection
Dynamic power management mode. The DDR memory controller can reduce power consumption
by negating the SDRAM CKE signal when no transactions are pending to the SDRAM.
Auto-precharge mode. Clearing DDR_SDRAM_INTERVAL[BSTOPRE] causes the memory
controller to issue an auto-precharge command with every read or write transaction.
Auto-precharge mode can be enabled for separate chip selects by setting
CSn_CONFIG[AP_n_EN].
Memory interface signals
Clock signals
Debug signals
External Signal Descriptions
shows how DDR memory controller external signals are grouped. The device hardware
Modes of Operation
Signals Overview
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
MDQ[0:63]
MDQS[0:8]
MDQS[0:8]
MECC[0:7]
MBA[2:0]
MA[15:0]
MCAS
Name
Table 9-1. DDR Memory Interface Signal Summary
Data bus
Data strobes
Complement data strobes
Error checking and correcting
Column address strobe
Address bus
Logical bank address
Function/Description
All zeros
All zeros
All zeros
All zeros
All zeros
All ones
Reset
One
Pins
64
16
9
9
8
1
3
I/O
I/O
I/O
I/O
I/O
O
O
O
DDR Memory Controller
9-3